//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// memory_sram.v
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// memory_sram.v
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//
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//
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// Abstract:
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// Abstract:
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// sram memory for simulation
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// sram memory for simulation
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module memory_sram (
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module memory_sram (
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clk,
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clk,
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adr,
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adr,
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din,
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din,
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be,
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be,
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dout,
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dout,
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rdb,
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rdb,
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wrb,
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wrb,
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rstb
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rstb
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);
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);
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/////////////////////////////////////
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/////////////////////////////////////
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// parameter
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// parameter
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////////////////////////////////////
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////////////////////////////////////
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parameter P_ADRS_WIDTH = 22;
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parameter P_ADRS_WIDTH = 22;
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parameter P_DATA_WIDTH = 32;
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parameter P_DATA_WIDTH = 32;
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parameter P_BE_WIDTH = P_DATA_WIDTH/8;
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parameter P_BE_WIDTH = P_DATA_WIDTH/8;
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/////////////////////////////////////
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/////////////////////////////////////
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// Port Definition
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// Port Definition
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////////////////////////////////////
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////////////////////////////////////
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input clk;
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input clk;
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input [P_ADRS_WIDTH-1:0]
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input [P_ADRS_WIDTH-1:0]
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adr;
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adr;
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input [P_DATA_WIDTH-1:0]
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input [P_DATA_WIDTH-1:0]
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din;
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din;
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input [P_BE_WIDTH-1:0]
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input [P_BE_WIDTH-1:0]
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be;
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be;
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output [P_DATA_WIDTH-1:0]
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output [P_DATA_WIDTH-1:0]
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dout;
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dout;
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input rdb;
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input rdb;
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input wrb;
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input wrb;
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input rstb;
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input rstb;
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/////////////////////////////////////
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/////////////////////////////////////
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// reg
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// reg
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////////////////////////////////////
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////////////////////////////////////
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// memory instance
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// memory instance
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reg [31:0] mem[0:(1 << P_ADRS_WIDTH)-1];
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reg [31:0] mem[0:(1 << P_ADRS_WIDTH)-1];
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reg [P_DATA_WIDTH-1:0]
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reg [P_DATA_WIDTH-1:0]
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r_dout_1z;
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r_dout_1z;
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reg [P_DATA_WIDTH-1:0]
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reg [P_DATA_WIDTH-1:0]
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r_dout_2z;
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r_dout_2z;
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/////////////////////////////////////
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/////////////////////////////////////
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// wire
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// wire
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////////////////////////////////////
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////////////////////////////////////
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wire [P_DATA_WIDTH-1:0]
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wire [P_DATA_WIDTH-1:0]
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w_dout;
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w_dout;
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wire [P_DATA_WIDTH-1:0]
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wire [P_DATA_WIDTH-1:0]
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w_din;
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w_din;
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/////////////////////////////////////
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/////////////////////////////////////
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// assign
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// assign
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////////////////////////////////////
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////////////////////////////////////
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assign w_dout = mem[adr];
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assign w_dout = mem[adr];
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assign w_din = f_new_data(din,be,mem[adr]);
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assign w_din = f_new_data(din,be,mem[adr]);
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assign dout = r_dout_2z;
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assign dout = r_dout_2z;
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/////////////////////////////////////
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/////////////////////////////////////
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// always
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// always
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////////////////////////////////////
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////////////////////////////////////
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integer i;
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integer i;
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initial begin
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initial begin
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for (i=0;i<(1 << P_ADRS_WIDTH);i=i+1)
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for (i=0;i<(1 << P_ADRS_WIDTH);i=i+1)
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mem[i] = 32'h00000000;
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mem[i] = 32'h00000000;
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (wrb == 1'b0) begin
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if (wrb == 1'b0) begin
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mem[adr] <= w_din;
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mem[adr] <= w_din;
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end
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end
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end
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end
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//`ifdef RTL_DEBUG
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//`ifdef RTL_DEBUG
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// always @(posedge clk) begin
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// always @(posedge clk) begin
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// if (wrb == 1'b0) begin
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// if (wrb == 1'b0) begin
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// $display("a4 a d = %h %h",adr,adr<<2,w_din);
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// $display("a4 a d = %h %h",adr,adr<<2,w_din);
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// end
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// end
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// end
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// end
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//`endif
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//`endif
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always @(posedge clk) begin
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always @(posedge clk) begin
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r_dout_1z <= w_dout;
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r_dout_1z <= w_dout;
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r_dout_2z <= r_dout_1z;
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r_dout_2z <= r_dout_1z;
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end
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end
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function [P_DATA_WIDTH-1:0] f_new_data;
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function [P_DATA_WIDTH-1:0] f_new_data;
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input [P_DATA_WIDTH-1:0] new_data;
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input [P_DATA_WIDTH-1:0] new_data;
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input [P_BE_WIDTH-1:0] be;
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input [P_BE_WIDTH-1:0] be;
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input [P_DATA_WIDTH-1:0] cur_data;
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input [P_DATA_WIDTH-1:0] cur_data;
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reg [P_DATA_WIDTH-1:0] result;
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reg [P_DATA_WIDTH-1:0] result;
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begin
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begin
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result = cur_data;
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result = cur_data;
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if (be[0]) result[7:0] = new_data[7:0];
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if (be[0]) result[7:0] = new_data[7:0];
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if (be[1]) result[15:8] = new_data[15:8];
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if (be[1]) result[15:8] = new_data[15:8];
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if (be[2]) result[23:16] = new_data[23:16];
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if (be[2]) result[23:16] = new_data[23:16];
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if (be[3]) result[31:24] = new_data[31:24];
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if (be[3]) result[31:24] = new_data[31:24];
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f_new_data = result;
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f_new_data = result;
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end
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end
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endfunction
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endfunction
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endmodule
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endmodule
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