//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// sram_slave_wb.v
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// sram_slave_wb.v
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//
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//
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// Abstract:
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// Abstract:
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// SRAM slave model with random read data delay.
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// SRAM slave model with random read data delay.
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// for WISHBONE bus simulation
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// for WISHBONE bus simulation
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module sram_slave_wb #(
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module sram_slave_wb #(
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parameter P_ADRS_WIDTH = 24,
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parameter P_ADRS_WIDTH = 24,
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parameter P_BE_WIDTH = 4,
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parameter P_BE_WIDTH = 4,
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parameter P_DATA_WIDTH = 32,
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parameter P_DATA_WIDTH = 32,
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parameter P_BLEN_WIDTH = 6,
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parameter P_BLEN_WIDTH = 6,
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parameter P_SEED = 'd0
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parameter P_SEED = 'd0
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)
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)
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(
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(
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input clk_core,
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input clk_core,
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input rst_x,
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input rst_x,
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input i_req,
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input i_req,
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input i_wr,
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input i_wr,
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input [P_ADRS_WIDTH-1:0] i_adrs,
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input [P_ADRS_WIDTH-1:0] i_adrs,
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input [P_BLEN_WIDTH-1:0] i_blen,
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input [P_BLEN_WIDTH-1:0] i_blen,
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output o_ack,
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output o_ack,
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input i_strw,
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input i_strw,
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input [P_BE_WIDTH-1:0] i_be,
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input [P_BE_WIDTH-1:0] i_be,
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input [P_DATA_WIDTH-1:0] i_dbw,
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input [P_DATA_WIDTH-1:0] i_dbw,
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output o_ackw,
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output o_ackw,
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output o_strr,
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output o_strr,
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output [P_DATA_WIDTH-1:0] o_dbr
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output [P_DATA_WIDTH-1:0] o_dbr
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);
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);
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//////////////////////////////////
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//////////////////////////////////
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// parameter
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// parameter
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//////////////////////////////////
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//////////////////////////////////
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localparam P_IDLE = 2'h0;
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localparam P_IDLE = 2'h0;
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localparam P_IN_WRITE = 2'h1;
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localparam P_IN_WRITE = 2'h1;
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localparam P_IN_READ = 2'h2;
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localparam P_IN_READ = 2'h2;
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localparam P_READ_DELAY = 'd15;
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localparam P_READ_DELAY = 'd15;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire w_req;
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wire w_req;
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wire [29:0]
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wire [29:0]
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w_fifo_cin;
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w_fifo_cin;
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wire [29:0]
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wire [29:0]
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w_fifo_cout;
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w_fifo_cout;
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wire [32+4-1:0]
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wire [32+4-1:0]
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w_fifo_din;
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w_fifo_din;
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wire [32+4-1:0]
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wire [32+4-1:0]
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w_fifo_dout;
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w_fifo_dout;
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wire w_cfifo_ack;
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wire w_cfifo_ack;
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wire w_dfifo_ack;
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wire w_dfifo_ack;
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wire w_read_req;
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wire w_read_req;
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wire [1:0] w_mcmd_f;
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wire [1:0] w_mcmd_f;
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wire [P_ADRS_WIDTH-1:0]
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wire [P_ADRS_WIDTH-1:0]
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w_maddr_f;
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w_maddr_f;
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wire [P_BLEN_WIDTH-1:0]
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wire [P_BLEN_WIDTH-1:0]
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w_mburst_length_f;
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w_mburst_length_f;
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wire w_command_valid;
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wire w_command_valid;
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wire w_burst_end;
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wire w_burst_end;
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wire [P_ADRS_WIDTH-1:0]
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wire [P_ADRS_WIDTH-1:0]
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w_sram_addr;
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w_sram_addr;
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wire [P_BE_WIDTH-1:0]
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wire [P_BE_WIDTH-1:0]
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w_sram_byte_en;
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w_sram_byte_en;
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wire [P_DATA_WIDTH-1:0]
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wire [P_DATA_WIDTH-1:0]
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w_sram_wdata;
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w_sram_wdata;
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wire [P_DATA_WIDTH-1:0]
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wire [P_DATA_WIDTH-1:0]
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w_sram_rdata;
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w_sram_rdata;
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wire w_sram_write;
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wire w_sram_write;
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wire w_datain_valid;
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wire w_datain_valid;
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wire w_dfifi_idle_ack;
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wire w_dfifi_idle_ack;
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wire [P_DATA_WIDTH-1:0] w_dbr;
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wire [P_DATA_WIDTH-1:0] w_dbr;
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wire w_act;
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wire w_act;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg [1:0] r_state;
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reg [1:0] r_state;
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reg [P_ADRS_WIDTH-1:0]
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reg [P_ADRS_WIDTH-1:0]
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r_maddr;
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r_maddr;
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reg [P_BLEN_WIDTH-1:0]
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reg [P_BLEN_WIDTH-1:0]
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r_mburst_length;
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r_mburst_length;
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reg r_read_req_1z;
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reg r_read_req_1z;
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reg r_read_req_2z;
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reg r_read_req_2z;
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reg [7:0] r_rand;
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reg [7:0] r_rand;
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reg [7:0] r_rand_rd;
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reg [7:0] r_rand_rd;
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reg [31:0] r_rand_seed;
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reg [31:0] r_rand_seed;
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reg [31:0] r_rand_rd_seed;
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reg [31:0] r_rand_rd_seed;
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wire w_ack;
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wire w_ack;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign w_sram_addr = (r_state == P_IDLE) ? i_adrs : r_maddr;
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assign w_sram_addr = (r_state == P_IDLE) ? i_adrs : r_maddr;
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assign w_sram_write = ((r_state == P_IN_WRITE)&i_strw);
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assign w_sram_write = ((r_state == P_IN_WRITE)&i_strw);
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assign w_ack = (r_state == P_IDLE) & w_act;
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assign w_ack = (r_state == P_IDLE) & w_act;
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assign o_ack = (r_state == P_IN_WRITE) | ((r_state == P_IN_READ) & o_strr);
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assign o_ack = (r_state == P_IN_WRITE) | ((r_state == P_IN_READ) & o_strr);
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assign o_ackw = 1'b1;
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assign o_ackw = 1'b1;
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assign w_read_req = (i_req & !i_wr & w_ack & w_act) ;
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assign w_read_req = (i_req & !i_wr & w_ack & w_act) ;
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assign w_act = (r_rand < 'h80);
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assign w_act = (r_rand < 'h80);
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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initial begin
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initial begin
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$display("RANDOM SEED = %d %m",P_SEED);
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$display("RANDOM SEED = %d %m",P_SEED);
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r_rand_seed = P_SEED;
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r_rand_seed = P_SEED;
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r_rand_rd_seed = P_SEED;
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r_rand_rd_seed = P_SEED;
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end
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end
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always @(negedge clk_core) begin
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always @(negedge clk_core) begin
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r_rand <= $random(r_rand_seed);
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r_rand <= $random(r_rand_seed);
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//r_rand <= 1;
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//r_rand <= 1;
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end
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end
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE : begin
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P_IDLE : begin
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if (i_req & w_act) begin
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if (i_req & w_act) begin
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if (i_wr == 'd1) begin
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if (i_wr == 'd1) begin
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r_state <= P_IN_WRITE;
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r_state <= P_IN_WRITE;
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end else begin
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end else begin
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//r_rand_rd <= 0;
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//r_rand_rd <= 0;
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r_rand_rd <= $random(r_rand_rd_seed);
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r_rand_rd <= $random(r_rand_rd_seed);
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r_state <= P_IN_READ;
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r_state <= P_IN_READ;
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end
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end
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end
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end
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end
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end
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P_IN_WRITE : begin
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P_IN_WRITE : begin
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if (i_strw) r_state <= P_IDLE;
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if (i_strw) r_state <= P_IDLE;
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end
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end
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P_IN_READ : begin
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P_IN_READ : begin
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if (o_strr) r_state <= P_IDLE;
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if (o_strr) r_state <= P_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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if ((r_state == P_IDLE)&i_req & w_act) begin
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if ((r_state == P_IDLE)&i_req & w_act) begin
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r_maddr <= i_adrs;
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r_maddr <= i_adrs;
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end
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end
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end
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end
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_read_req_1z <= 1'b0;
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r_read_req_1z <= 1'b0;
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r_read_req_2z <= 1'b0;
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r_read_req_2z <= 1'b0;
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end else begin
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end else begin
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r_read_req_1z <= w_read_req;
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r_read_req_1z <= w_read_req;
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r_read_req_2z <= r_read_req_1z;
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r_read_req_2z <= r_read_req_1z;
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end
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end
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end
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end
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//////////////////////////////////
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//////////////////////////////////
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// module instantiation
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// module instantiation
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//////////////////////////////////
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//////////////////////////////////
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// delay module
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// delay module
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rand_delay # (1,16) u_delay_strr (
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rand_delay # (1,16) u_delay_strr (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_en(r_read_req_2z),
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.i_en(r_read_req_2z),
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.i_delay(r_rand_rd),
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.i_delay(r_rand_rd),
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.i_data(r_read_req_2z),
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.i_data(r_read_req_2z),
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.o_data(),
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.o_data(),
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.o_en(o_strr)
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.o_en(o_strr)
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);
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);
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rand_delay #(P_DATA_WIDTH,16) u_delay_dbr (
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rand_delay #(P_DATA_WIDTH,16) u_delay_dbr (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_en(r_read_req_2z),
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.i_en(r_read_req_2z),
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.i_delay(r_rand_rd),
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.i_delay(r_rand_rd),
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.i_data(w_dbr),
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.i_data(w_dbr),
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.o_data(o_dbr),
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.o_data(o_dbr),
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.o_en()
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.o_en()
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);
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);
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memory_sram #(P_ADRS_WIDTH) u_memory (
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memory_sram #(P_ADRS_WIDTH) u_memory (
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.clk(clk_core),
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.clk(clk_core),
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.adr(w_sram_addr),
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.adr(w_sram_addr),
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.din(i_dbw),
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.din(i_dbw),
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.be(i_be),
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.be(i_be),
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.dout(w_dbr),
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.dout(w_dbr),
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.rdb(~w_read_req),
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.rdb(~w_read_req),
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.wrb(~w_sram_write),
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.wrb(~w_sram_write),
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.rstb(rst_x)
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.rstb(rst_x)
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);
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);
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endmodule
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endmodule
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