//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// tb_task.v
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// tb_task.v
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//
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//
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// Abstract:
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// Abstract:
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// simulation tasks
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// simulation tasks
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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task reg_write;
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task reg_write;
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input [7:0] adrs;
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input [7:0] adrs;
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input [3:0] be;
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input [3:0] be;
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input [31:0] wd;
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input [31:0] wd;
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begin
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begin
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s_wb_stb_i = 1;
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s_wb_stb_i = 1;
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s_wb_we_i = 1;
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s_wb_we_i = 1;
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s_wb_adr_i = adrs;
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s_wb_adr_i = adrs;
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s_wb_sel_i = be;
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s_wb_sel_i = be;
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s_wb_dat_i = wd;
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s_wb_dat_i = wd;
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@(posedge clk_core);
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@(posedge clk_core);
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while (!s_wb_ack_o)
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while (!s_wb_ack_o)
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@(posedge clk_core);
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@(posedge clk_core);
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s_wb_stb_i = 0;
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s_wb_stb_i = 0;
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@(posedge clk_core);
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@(posedge clk_core);
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end
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end
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endtask
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endtask
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task reg_read;
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task reg_read;
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input [7:0] adrs;
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input [7:0] adrs;
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output [31:0] rd;
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output [31:0] rd;
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begin
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begin
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s_wb_stb_i = 1;
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s_wb_stb_i = 1;
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s_wb_we_i = 0;
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s_wb_we_i = 0;
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s_wb_adr_i = adrs;
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s_wb_adr_i = adrs;
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@(posedge clk_core);
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@(posedge clk_core);
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while (!s_wb_ack_o)
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while (!s_wb_ack_o)
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@(posedge clk_core);
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@(posedge clk_core);
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s_wb_stb_i = 0;
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s_wb_stb_i = 0;
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rd = s_wb_dat_o;
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rd = s_wb_dat_o;
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@(posedge clk_core);
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@(posedge clk_core);
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end
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end
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endtask
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endtask
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`else
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`else
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task reg_write;
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task reg_write;
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input [7:0] adrs;
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input [7:0] adrs;
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input [3:0] be;
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input [3:0] be;
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input [31:0] wd;
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input [31:0] wd;
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begin
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begin
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i_req_s = 1;
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i_req_s = 1;
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i_wr_s = 1;
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i_wr_s = 1;
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i_adrs_s = adrs;
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i_adrs_s = adrs;
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i_be_s = be;
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i_be_s = be;
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i_dbw_s = wd;
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i_dbw_s = wd;
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@(posedge clk_core);
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@(posedge clk_core);
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while (!o_ack_s)
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while (!o_ack_s)
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@(posedge clk_core);
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@(posedge clk_core);
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i_req_s = 0;
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i_req_s = 0;
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@(posedge clk_core);
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@(posedge clk_core);
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end
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end
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endtask
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endtask
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task reg_read;
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task reg_read;
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input [7:0] adrs;
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input [7:0] adrs;
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output [31:0] rd;
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output [31:0] rd;
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begin
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begin
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i_req_s = 1;
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i_req_s = 1;
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i_wr_s = 0;
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i_wr_s = 0;
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i_adrs_s = adrs;
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i_adrs_s = adrs;
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@(posedge clk_core);
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@(posedge clk_core);
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while (!o_ack_s)
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while (!o_ack_s)
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@(posedge clk_core);
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@(posedge clk_core);
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while (!o_strr_s) begin
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while (!o_strr_s) begin
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i_req_s = 0;
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i_req_s = 0;
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@(posedge clk_core);
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@(posedge clk_core);
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end
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end
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rd = o_dbr_s;
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rd = o_dbr_s;
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@(posedge clk_core);
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@(posedge clk_core);
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end
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end
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endtask
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endtask
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`endif
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`endif
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