//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores SPI Interface Module ////
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//// xSPI Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the xspi project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// https://opencores.org/projects/xspi ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// xspi definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module spi_if
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module xspi_if
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(
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(
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clk,
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clk,
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reset_n,
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reset_n,
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// towards ctrl i/f
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// towards ctrl i/f
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sck_pe,
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sck_pe,
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sck_int,
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sck_int,
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cs_int_n,
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cs_int_n,
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byte_in,
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byte_in,
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load_byte,
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load_byte,
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byte_out,
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byte_out,
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shift_out,
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shift_out,
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shift_in,
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shift_in,
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cfg_tgt_sel,
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cfg_tgt_sel,
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sck,
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sck,
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so,
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so,
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si,
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si,
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cs_n
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cs_n
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);
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);
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input clk,reset_n;
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input clk,reset_n;
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input sck_pe;
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input sck_pe;
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input sck_int,cs_int_n;
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input sck_int,cs_int_n;
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input load_byte;
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input load_byte;
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input [1:0] cfg_tgt_sel;
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input [1:0] cfg_tgt_sel;
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input [7:0] byte_out;
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input [7:0] byte_out;
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input shift_out,shift_in;
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input shift_out,shift_in;
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output [7:0] byte_in;
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output [7:0] byte_in;
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output sck,so;
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output sck,so;
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output [3:0] cs_n;
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output [3:0] cs_n;
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input si;
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input si;
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reg [7:0] so_reg;
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reg [7:0] so_reg;
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reg [7:0] si_reg;
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reg [7:0] si_reg;
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wire [7:0] byte_out;
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wire [7:0] byte_out;
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wire sck;
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wire sck;
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reg so;
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reg so;
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wire [3:0] cs_n;
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wire [3:0] cs_n;
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//Output Shift Register
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//Output Shift Register
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if(!reset_n) begin
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if(!reset_n) begin
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so_reg <= 8'h00;
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so_reg <= 8'h00;
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so <= 1'b0;
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so <= 1'b0;
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end
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end
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else begin
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else begin
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if(load_byte) begin
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if(load_byte) begin
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so_reg <= byte_out;
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so_reg <= byte_out;
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if(shift_out) begin
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if(shift_out) begin
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// Handling backto back case :
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// Handling backto back case :
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// Last Transfer bit + New Trasfer Load
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// Last Transfer bit + New Trasfer Load
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so <= so_reg[7];
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so <= so_reg[7];
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end
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end
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end // if (load_byte)
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end // if (load_byte)
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else begin
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else begin
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if(shift_out) begin
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if(shift_out) begin
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so <= so_reg[7];
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so <= so_reg[7];
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so_reg <= {so_reg[6:0],1'b0};
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so_reg <= {so_reg[6:0],1'b0};
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end // if (shift_out)
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end // if (shift_out)
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end // else: !if(load_byte)
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end // else: !if(load_byte)
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end // else: !if(!reset_n)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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end // always @ (posedge clk or negedge reset_n)
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// Input shift register
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// Input shift register
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if(!reset_n) begin
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if(!reset_n) begin
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si_reg <= 8'h0;
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si_reg <= 8'h0;
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end
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end
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else begin
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else begin
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if(sck_pe & shift_in) begin
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if(sck_pe & shift_in) begin
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si_reg[7:0] <= {si_reg[6:0],si};
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si_reg[7:0] <= {si_reg[6:0],si};
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end // if (sck_pe & shift_in)
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end // if (sck_pe & shift_in)
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end // else: !if(!reset_n)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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end // always @ (posedge clk or negedge reset_n)
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assign byte_in[7:0] = si_reg[7:0];
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assign byte_in[7:0] = si_reg[7:0];
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assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1;
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assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1;
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assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1;
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assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1;
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assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1;
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assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1;
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assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1;
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assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1;
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assign sck = sck_int;
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assign sck = sck_int;
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endmodule
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endmodule
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