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//////////////////////////////////////////////////////////////////////
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//// ////
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//// XTEA IP Core ////
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//// ////
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//// This file is part of the xtea project ////
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//// http://www.opencores.org/projects.cgi/web/xtea/overview ////
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//// ////
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//// An implementation of the XTEA encryption algorithm. ////
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//// ////
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//// TODO: ////
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//// * Write a spec ////
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//// * Wishbone compliance ////
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//// ////
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//// Author: David Johnson, dj@david-web.co.uk ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006 David Johnson ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, write to the ////
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//// Free Software Foundation, Inc., 51 Franklin Street, Fifth ////
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//// Floor, Boston, MA 02110-1301 USA ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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module xtea(clock, reset, mode, data_in1, data_in2, key_in, data_out1, data_out2, all_done);
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parameter s0 = 8'd0, s1 = 8'd1, s2 = 8'd2, s3 = 8'd3, s4 = 8'd4, s5 = 8'd5, s6 = 8'd6, s7 = 8'd7, s8 = 8'd8, s9 = 8'd9, s10 = 8'd10,
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s11 = 8'd11, s12 = 8'd12, s13 = 8'd13, s14 = 8'd14, s15 = 8'd15, s16 = 8'd16, s17 = 8'd17;
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input clock, reset, mode;
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input[31:0] data_in1, data_in2;
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input[127:0] key_in;
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output[31:0] data_out1, data_out2;
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output all_done;
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wire clock, reset;
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wire[31:0] data_in1, data_in2;
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wire[127:0] key_in;
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reg all_done, while_flag, modereg;
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reg[1:0] selectslice;
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reg[7:0] state;
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reg[7:0] x;
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reg[31:0] data_out1, data_out2, sum, workunit1, workunit2, delta;
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always @(posedge clock or posedge reset)
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begin
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if (reset)
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//reset state
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state = s0;
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else begin
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case (state)
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s0: state = s1;
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s1: state = s2;
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s2: state = s3;
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s3: state = while_flag ? s4 : s14;
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s4: state = modereg ? s10 : s5;
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s5: state = s6;
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s6: state = s7;
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s7: state = s8;
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s8: state = s9;
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s9: state = s2;
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s10: state = s11;
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s11: state = s12;
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s12: state = s13;
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s13: state = s14;
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s14: state = s2;
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s15: state = s16;
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s16: state = s17;
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s17: state = s17;
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default: state = 4'bxxxx;
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endcase
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end
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end
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always @(posedge clock or posedge reset)
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begin
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if (reset) begin
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//reset all our outputs and registers
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data_out1 = 32'h00000000;
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data_out2 = 32'h00000000;
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x = 8'b00000000;
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sum = 32'h00000000;
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while_flag = 1'b0;
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workunit1 = 32'h00000000;
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workunit2 = 32'h00000000;
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selectslice = 1'b0;
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all_done = 1'b0;
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delta = 32'h00000000;
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modereg = 1'b0;
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end
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else begin
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case (state)
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s1: begin
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//store input values to registers in case they're not stable
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workunit1 = data_in1;
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workunit2 = data_in2;
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delta = 32'h9E3779B9;
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sum = 32'hc6ef3720;
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modereg = mode;
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end
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s2: if (x < 8'd32) while_flag = 1'b1; else while_flag = 1'b0;
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s3: begin
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//This null state was necessary to fix a timing issue.
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//s2 sets while_flag and previously the control path read it in the same state
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//(but in the next clock cycle), however the reg wasn't set when we tried to
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//read it, so this state was inserted to add a delay. This was when running @25MHz.
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//FIXME: there's got to be a better solution to this...
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end
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s4: begin
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//This state does nothing in the data path; it's used for an if statement in the
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//control path.
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end
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/* States 5-9 used for decipher operations */
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s5: selectslice = (sum >> 32'd11 & 32'd3);
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s6: case (selectslice)
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2'b00: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
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2'b01: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
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2'b10: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
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2'b11: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
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default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
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endcase
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s7: sum = sum - delta;
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s8: selectslice = (sum & 32'd3);
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s9: begin
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case (selectslice)
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2'b00: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
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2'b01: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
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2'b10: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
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2'b11: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
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default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
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endcase
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x = x + 1'b1;
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end
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/* States 10-14 used for encipher operations */
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s10: selectslice = (sum & 32'd3);
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s11: case (selectslice)
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2'b00: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
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2'b01: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
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2'b10: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
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2'b11: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
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default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
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endcase
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s12: sum = sum + delta;
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s13: selectslice = (sum >> 32'd11 & 32'd3);
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s14: begin
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case (selectslice)
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2'b00: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
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2'b01: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
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2'b10: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
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2'b11: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
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default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
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endcase
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x = x + 1'b1;
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end
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s15: begin
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//This state was added to fix a timing issue.
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//Same issue as above - trying to read workunit1 & workunit2 before they've settled.
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end
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s16: begin
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//set the outputs to the working registers
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data_out1 = workunit1;
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data_out2 = workunit2;
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end
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s17: all_done = 1'b1;
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default: begin
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data_out1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
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data_out2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
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end
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endcase
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end
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end
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endmodule
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