| Line 30... |
Line 30... |
##
|
##
|
################################################################################
|
################################################################################
|
##
|
##
|
##
|
##
|
.PHONY: all
|
.PHONY: all
|
all: datestamp verilated bit
|
all: datestamp verilated bit sw
|
# Could also depend upon load, if desired, but not necessary
|
# Could also depend upon load, if desired, but not necessary
|
BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
|
BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
|
RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
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RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
|
NOTES := `find . -name "*.txt"` `find . -name "*.html"`
|
NOTES := `find . -name "*.txt"` `find . -name "*.html"`
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SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
|
SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
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| Line 44... |
Line 44... |
xilinx/xula.ut xilinx/Makefile
|
xilinx/xula.ut xilinx/Makefile
|
BIN := `find xilinx -name "*.bit"`
|
BIN := `find xilinx -name "*.bit"`
|
CONSTRAINTS := xula.ucf
|
CONSTRAINTS := xula.ucf
|
YYMMDD:=`date +%Y%m%d`
|
YYMMDD:=`date +%Y%m%d`
|
|
|
datestamp: $(YYMMDD)-build.v
|
.PHONY: datestamp
|
$(YYMMDD)-build.v:
|
datestamp:
|
-rm -rf 2*-build.v
|
bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then perl xilinx/mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi'
|
perl xilinx/mkdatev.pl > $(YYMMDD)-build.v
|
bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; ln -fs ../$(YYMMDD)-build.v builddate.v; fi'
|
cd rtl; ln -fs ../$(YYMMDD)-build.v builddate.v
|
|
|
|
.PHONY: archive
|
.PHONY: archive
|
archive:
|
archive:
|
tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
|
tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
|
|
|
.PHONY: tare
|
|
tare:
|
|
echo tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
|
|
|
|
.PHONY: verilated
|
.PHONY: verilated
|
verilated:
|
verilated:
|
cd rtl ; make
|
cd rtl ; $(MAKE) --no-print-directory
|
|
|
|
.PHONY: sw
|
|
sw:
|
|
cd sw ; $(MAKE) --no-print-directory
|
|
|
.PHONY: bit
|
.PHONY: bit
|
bit:
|
bit:
|
cd xilinx ; make xula.bit
|
cd xilinx ; $(MAKE) --no-print-directory xula.bit
|
|
|
.PHONY: load
|
.PHONY: load
|
load: bit
|
load: bit
|
xsload -b xula2-lx25 --fpga xilinx/xula.bit
|
xsload -b xula2-lx25 --fpga xilinx/xula.bit
|
|
|
| Line 76... |
Line 75... |
xload:
|
xload:
|
xsload -b xula2-lx25 --fpga xilinx/toplevel.bit
|
xsload -b xula2-lx25 --fpga xilinx/toplevel.bit
|
|
|
.PHONY: timing
|
.PHONY: timing
|
timing:
|
timing:
|
cd xilinx ; make timing
|
cd xilinx ; $(MAKE) --no-print-directory timing
|
|
|
|
|
