| Line 87... |
Line 87... |
// Position #2: The ICAP configuration scope, could also be the SDCard scope
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// Position #2: The ICAP configuration scope, could also be the SDCard scope
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// depending on how we configure ourselves here
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// depending on how we configure ourselves here
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//
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//
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`ifdef XULA25
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`ifdef XULA25
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`ifdef FANCY_ICAP_ACCESS
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`ifdef FANCY_ICAP_ACCESS
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`define CFG_SCOPE // Only defined if we have the access ...
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// `define CFG_SCOPE // Only defined if we have the access ...
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`else
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`else
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`ifdef SDCARD_ACCESS
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`ifdef SDCARD_ACCESS
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`define SDCARD_SCOPE
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// `define SDCARD_SCOPE
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`endif
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`endif
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`endif
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`endif
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`endif
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`endif
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//
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//
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// Position #3: The SDRAM scope / UART scope (never both)
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// Position #3: The SDRAM scope / UART scope (never both)
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| Line 107... |
Line 107... |
`ifdef INCLUDE_ZIPCPU
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`ifdef INCLUDE_ZIPCPU
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`ifdef VERILATOR
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`ifdef VERILATOR
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`define ZIP_SCOPE
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`define ZIP_SCOPE
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`else // VERILATOR
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`else // VERILATOR
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`ifdef XULA25
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`ifdef XULA25
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`define ZIP_SCOPE
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// `define ZIP_SCOPE
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`endif // XULA25
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`endif // XULA25
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`endif // VERILATOR
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`endif // VERILATOR
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`endif // INCLUDE_ZIPCPU
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`endif // INCLUDE_ZIPCPU
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|
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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| Line 232... |
Line 232... |
`ifdef ZIP_SCOPE
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`ifdef ZIP_SCOPE
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, zip_debug
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, zip_debug
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`endif
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`endif
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);
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);
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`else
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`else
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zipbones #(24'h2000,ZA,8,1)
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zipbones #(24'h2000,ZA,10,1)
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zippy(i_clk, 1'b0,
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zippy(i_clk, 1'b0,
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// Zippys wishbone interface
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// Zippys wishbone interface
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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zip_ack, zip_stall, dwb_idata, zip_err,
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zip_ack, zip_stall, dwb_idata, zip_err,
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w_interrupt, zip_cpu_int,
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w_interrupt, zip_cpu_int,
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| Line 331... |
Line 331... |
assign dwb_addr = wbu_addr;
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assign dwb_addr = wbu_addr;
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assign dwb_odata = wbu_data;
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assign dwb_odata = wbu_data;
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assign dwb_we = wbu_we;
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assign dwb_we = wbu_we;
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assign dwb_stb = (wbu_stb);
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assign dwb_stb = (wbu_stb);
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assign dwb_cyc = (wbu_cyc);
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assign dwb_cyc = (wbu_cyc);
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assign wb_cyc = dwb_cyc;
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assign wb_stb = dwb_stb;
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assign wb_we = dwb_we;
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assign wb_addr = dwb_addr;
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assign wb_data = dwb_odata;
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assign wbu_ack = dwb_ack;
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assign wbu_ack = dwb_ack;
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assign wbu_stall = dwb_stall;
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assign wbu_stall = dwb_stall;
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assign dwb_idata = wb_idata;
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assign dwb_idata = wb_idata;
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assign wbu_err = dwb_err;
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assign wbu_err = dwb_err;
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`endif
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`endif
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