| Line 45... |
Line 45... |
// Configuration question #1
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// Configuration question #1
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//
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//
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// What innate capabilities are built into the board?
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// What innate capabilities are built into the board?
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//
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//
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`define INCLUDE_ZIPCPU
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`define INCLUDE_ZIPCPU
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// `define NO_ZIP_WBU_DELAY
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// Without the ZipCPU competing for the bus, we don't need to delay it by a
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// cycle.
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`ifndef INCLUDE_ZIPCPU
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`define NO_ZIP_WBU_DELAY
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`endif
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`ifdef VERILATOR
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`define NO_ZIP_WBU_DELAY
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`endif
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM
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`ifndef VERILATOR
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`ifndef VERILATOR
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`ifndef XULA25
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`ifndef XULA25
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// `define FANCY_ICAP_ACCESS
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// `define FANCY_ICAP_ACCESS
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`endif
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`endif
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| Line 165... |
Line 174... |
wire w_interrupt;
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wire w_interrupt;
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// Oh, and the debug control for the ZIP CPU
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// Oh, and the debug control for the ZIP CPU
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wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
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wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
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assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
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assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
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wire [31:0] zip_dbg_data;
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wire [31:0] zip_dbg_data;
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wire wbu_dbg;
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wbubus genbus(i_clk, i_rx_stb, i_rx_data,
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wbubus genbus(i_clk, i_rx_stb, i_rx_data,
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wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
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wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
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`ifdef INCLUDE_ZIPCPU
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`ifdef INCLUDE_ZIPCPU
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((~wbu_zip_sel)&&(wbu_ack))
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((~wbu_zip_sel)&&(wbu_ack))
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||((wbu_zip_sel)&&(zip_dbg_ack)),
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||((wbu_zip_sel)&&(zip_dbg_ack)),
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| Line 178... |
Line 188... |
`else
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`else
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wbu_ack, wbu_stall,
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wbu_ack, wbu_stall,
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wbu_err, dwb_idata,
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wbu_err, dwb_idata,
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`endif
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`endif
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w_interrupt,
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w_interrupt,
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o_tx_stb, o_tx_data, i_tx_busy);
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o_tx_stb, o_tx_data, i_tx_busy,
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wbu_dbg);
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//
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//
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//
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//
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// Second BUS master source: The ZipCPU
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// Second BUS master source: The ZipCPU
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| Line 197... |
Line 208... |
wire [31:0] dwb_addr, dwb_odata;
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wire [31:0] dwb_addr, dwb_odata;
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wire [8:0] w_ints_to_zip_cpu;
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wire [8:0] w_ints_to_zip_cpu;
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`ifdef INCLUDE_ZIPCPU
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`ifdef INCLUDE_ZIPCPU
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`ifdef XULA25
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`ifdef XULA25
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wire [31:0] zip_debug;
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wire [31:0] zip_debug;
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zipsystem #(24'h2000,ZA,8,1,9)
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zipsystem #(24'h2000,ZA,9,1,9)
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zippy(i_clk, 1'b0,
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zippy(i_clk, 1'b0,
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// Zippys wishbone interface
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// Zippys wishbone interface
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
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zip_ack, zip_stall, dwb_idata, zip_err,
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zip_ack, zip_stall, dwb_idata, zip_err,
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w_ints_to_zip_cpu, zip_cpu_int,
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w_ints_to_zip_cpu, zip_cpu_int,
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| Line 259... |
Line 270... |
wbu_ack, wbu_stall, wbu_err,
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wbu_ack, wbu_stall, wbu_err,
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// Common bus returns
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// Common bus returns
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dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
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dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
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dwb_ack, dwb_stall, dwb_err);
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dwb_ack, dwb_stall, dwb_err);
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//
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//
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// And because the ZIP CPU and the Arbiter create an unacceptable
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// delay, we fail timing. So we add in a delay cycle ...
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//
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//
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`ifdef NO_ZIP_WBU_DELAY
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assign wb_cyc = dwb_cyc;
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assign wb_stb = dwb_stb;
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assign wb_we = dwb_we;
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assign wb_addr = dwb_addr;
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assign wb_data = dwb_odata;
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assign dwb_idata = wb_idata;
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assign dwb_ack = wb_ack;
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assign dwb_stall = wb_stall;
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assign dwb_err = wb_err;
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`else
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`else
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busdelay wbu_zip_delay(i_clk,
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dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
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dwb_ack, dwb_stall, dwb_idata, dwb_err,
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wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
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wb_ack, wb_stall, wb_idata, wb_err);
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`endif
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`else // if no ZIP_CPU
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assign zip_cyc = 1'b0;
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assign zip_cyc = 1'b0;
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assign zip_stb = 1'b0;
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assign zip_stb = 1'b0;
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assign zip_we = 1'b0;
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assign zip_we = 1'b0;
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assign zip_cpu_int = 1'b0;
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assign zip_cpu_int = 1'b0;
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assign zip_addr = 32'h000;
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assign zip_addr = 32'h000;
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| Line 287... |
Line 323... |
assign dwb_idata = wb_idata;
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assign dwb_idata = wb_idata;
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assign wbu_err = dwb_err;
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assign wbu_err = dwb_err;
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`endif
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`endif
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//
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//
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// And because the ZIP CPU and the Arbiter create an unacceptable
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// delay, we fail timing. So we add in a delay cycle ...
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//
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//
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`ifdef NO_ZIP_WBU_DELAY
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assign wb_cyc = dwb_cyc;
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assign wb_stb = dwb_stb;
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assign wb_we = dwb_we;
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assign wb_addr = dwb_addr;
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assign wb_data = dwb_odata;
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assign dwb_idata = wb_idata;
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assign dwb_ack = wb_ack;
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assign dwb_stall = wb_stall;
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assign dwb_err = wb_err;
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`else
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busdelay wbu_zip_delay(i_clk,
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dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
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dwb_ack, dwb_stall, dwb_idata, dwb_err,
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wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
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wb_ack, wb_stall, wb_idata, wb_err);
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`endif
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wire io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
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wire io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
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cfg_sel, mem_sel, sdram_sel, sdcard_sel,
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cfg_sel, mem_sel, sdram_sel, sdcard_sel,
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none_sel, many_sel, io_bank;
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none_sel, many_sel, io_bank;
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wire io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
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wire io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
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| Line 473... |
Line 484... |
// audio rate can be adjusted (1), or whether it is fixed within the
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// audio rate can be adjusted (1), or whether it is fixed within the
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// build (0).
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// build (0).
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`ifdef XULA25
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`ifdef XULA25
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wbpwmaudio #(16'd1813,1) // 44.1 kHz, user adjustable
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wbpwmaudio #(16'd1813,1) // 44.1 kHz, user adjustable
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`else
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`else
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wbpwmaudio #(16'h2710,0,16) // 8 kHz, fixed audio rate
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wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
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`endif
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`endif
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pwmdev(i_clk,
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pwmdev(i_clk,
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wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
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wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
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wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
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wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
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//
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//
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// FLASH MEMORY CONFIGURATION ACCESS
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// FLASH MEMORY CONFIGURATION ACCESS
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//
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//
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wire flash_cs_n, flash_sck, flash_mosi;
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wire flash_cs_n, flash_sck, flash_mosi;
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wire spi_user, sdcard_grant, flash_grant;
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wire spi_user, sdcard_grant, flash_grant;
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