| Line 101... |
Line 101... |
// // 4'h4: // R/O Power count
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// // 4'h4: // R/O Power count
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// // 4'h5: // RTC count
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// // 4'h5: // RTC count
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// default: begin end
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// default: begin end
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// endcase
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// endcase
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// end else
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// end else
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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if ((i_wb_stb)&&(~i_wb_we))
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begin
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begin
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casez(i_wb_addr[3:0])
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casez(i_wb_addr[3:0])
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4'h01: r_wb_data <= `DATESTAMP;
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4'h01: r_wb_data <= `DATESTAMP;
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4'h02: r_wb_data <= ictrl_data;
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4'h02: r_wb_data <= ictrl_data;
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4'h03: r_wb_data <= i_bus_err_addr;
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4'h03: r_wb_data <= i_bus_err_addr;
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| Line 129... |
Line 129... |
wire [8:0] interrupt_vector;
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wire [8:0] interrupt_vector;
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assign interrupt_vector = { tm_int,
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assign interrupt_vector = { tm_int,
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i_uart_tx_int, i_uart_rx_int, i_pwm_int, gpio_int,
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i_uart_tx_int, i_uart_rx_int, i_pwm_int, gpio_int,
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i_scop_int, i_flash_int, ck_int, brd_interrupts[0] };
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i_scop_int, i_flash_int, ck_int, brd_interrupts[0] };
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icontrol #(9) intcontroller(i_clk, 1'b0,
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icontrol #(9) intcontroller(i_clk, 1'b0,
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((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
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((i_wb_stb)&&(i_wb_we)
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&&(i_wb_addr==5'h2)), i_wb_data,
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&&(i_wb_addr==5'h2)), i_wb_data,
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ictrl_data, interrupt_vector,
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ictrl_data, interrupt_vector,
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o_interrupt);
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o_interrupt);
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|
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/*
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/*
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