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[/] [xulalx25soc/] [trunk/] [rtl/] [lldspi.v] - Diff between revs 2 and 74

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Rev 2 Rev 74
Line 41... Line 41...
`define SPI_BITS        3'h2
`define SPI_BITS        3'h2
`define SPI_READY       3'h3
`define SPI_READY       3'h3
`define SPI_HOLDING     3'h4
`define SPI_HOLDING     3'h4
`define SPI_STOP        3'h5
`define SPI_STOP        3'h5
`define SPI_STOP_B      3'h6
`define SPI_STOP_B      3'h6
 
`define SPI_WAIT        3'h7
 
 
// Modes
// Modes
// `define      SPI_MOD_SPI     2'b00
// `define      SPI_MOD_SPI     2'b00
// `define      QSPI_MOD_QOUT   2'b10
// `define      QSPI_MOD_QOUT   2'b10
// `define      QSPI_MOD_QIN    2'b11
// `define      QSPI_MOD_QIN    2'b11
Line 52... Line 53...
module  lldspi(i_clk,
module  lldspi(i_clk,
                // Module interface
                // Module interface
                i_wr, i_hold, i_word, i_len,
                i_wr, i_hold, i_word, i_len,
                        o_word, o_valid, o_busy,
                        o_word, o_valid, o_busy,
                // QSPI interface
                // QSPI interface
                o_sck, o_cs_n, i_cs_n, o_mosi, i_miso);
                o_sck, o_cs_n, i_cs_n, o_mosi, i_miso,
 
                // Bus grant information
 
                i_bus_grant);
        input                   i_clk;
        input                   i_clk;
        // Chip interface
        // Chip interface
        //      Can send info
        //      Can send info
        //              i_hold = 0, i_wr = 1,
        //              i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_word = { 1'b0, 32'info to send },
Line 70... Line 73...
        output  reg             o_sck;
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg             o_cs_n;
        input                   i_cs_n; // Feedback from the arbiter
        input                   i_cs_n; // Feedback from the arbiter
        output  reg             o_mosi;
        output  reg             o_mosi;
        input                   i_miso;
        input                   i_miso;
 
        // Bus grant
 
        input                   i_bus_grant;
 
 
        reg     [5:0]    spi_len;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        reg     [2:0]    state;
Line 91... Line 96...
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b0;
                        o_busy  <= 1'b0;
                        if (i_wr)
                        if (i_wr)
                        begin
                        begin
                                r_word <= i_word;
                                r_word <= i_word;
                                state <= `SPI_START;
                                state <= `SPI_WAIT;
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                                o_cs_n <= 1'b0;
                                o_cs_n <= 1'b0;
                                o_busy <= 1'b1;
                                o_busy <= 1'b1;
                                o_sck <= 1'b1;
                                o_sck <= 1'b1;
                        end
                        end
 
                end else if (state == `SPI_WAIT)
 
                begin
 
                        if (i_bus_grant)
 
                                state <= `SPI_START;
                end else if (state == `SPI_START)
                end else if (state == `SPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                begin // We come in here with sck high, stay here 'til sck is low
                        if (~i_cs_n) // Wait 'til the bus has been granted
                        if (~i_cs_n) // Wait 'til the bus has been granted
                                o_sck <= 1'b0;
                                o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        if (o_sck == 1'b0)

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