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Line 105... |
`define RXU_BREAK 4'hd
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`define RXU_BREAK 4'hd
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`define RXU_RESET_IDLE 4'he
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`define RXU_RESET_IDLE 4'he
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`define RXU_IDLE 4'hf
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`define RXU_IDLE 4'hf
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module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
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module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
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o_parity_err, o_frame_err, o_ck_uart);
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o_parity_err, o_frame_err);
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// parameter // CLOCKS_PER_BAUD = 25'd004340,
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// parameter // CLOCKS_PER_BAUD = 25'd004340,
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// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
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// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
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// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
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// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
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// 8 data bits, no parity, (at least 1) stop bit
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// 8 data bits, no parity, (at least 1) stop bit
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input i_clk, i_reset;
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input i_clk, i_reset;
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Line 117... |
input i_uart;
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input i_uart;
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output reg o_wr;
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output reg o_wr;
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output reg [7:0] o_data;
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output reg [7:0] o_data;
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output reg o_break;
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output reg o_break;
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output reg o_parity_err, o_frame_err;
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output reg o_parity_err, o_frame_err;
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output wire o_ck_uart;
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity;
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Line 142... |
begin
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begin
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q_uart <= i_uart;
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q_uart <= i_uart;
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qq_uart <= q_uart;
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qq_uart <= q_uart;
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ck_uart <= qq_uart;
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ck_uart <= qq_uart;
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end
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end
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assign o_ck_uart = ck_uart;
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// assign o_ck_uart = ck_uart;
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reg [27:0] chg_counter;
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reg [27:0] chg_counter;
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initial chg_counter = 28'h00;
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initial chg_counter = 28'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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