| Line 143... |
Line 143... |
reg r_cmd_sent;
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reg r_cmd_sent;
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reg [31:0] fifo_a_reg, fifo_b_reg;
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reg [31:0] fifo_a_reg, fifo_b_reg;
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//
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//
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reg q_busy;
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reg q_busy;
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//
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//
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reg [7:0] fifo_a_mem[((1<<(LGFIFOLN+2))-1):0];
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reg [7:0] fifo_a_mem_0[0:((1<<LGFIFOLN)-1)],
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reg [7:0] fifo_b_mem[((1<<(LGFIFOLN+2))-1):0];
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fifo_a_mem_1[0:((1<<LGFIFOLN)-1)],
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fifo_a_mem_2[0:((1<<LGFIFOLN)-1)],
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fifo_a_mem_3[0:((1<<LGFIFOLN)-1)],
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fifo_b_mem_0[0:((1<<LGFIFOLN)-1)],
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fifo_b_mem_1[0:((1<<LGFIFOLN)-1)],
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fifo_b_mem_2[0:((1<<LGFIFOLN)-1)],
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fifo_b_mem_3[0:((1<<LGFIFOLN)-1)];
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reg [(LGFIFOLN-1):0] fifo_wb_addr;
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reg [(LGFIFOLN-1):0] fifo_wb_addr;
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reg [(LGFIFOLN+1):0] rd_fifo_sd_addr;
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reg [(LGFIFOLN+1):0] rd_fifo_sd_addr;
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reg [(LGFIFOLN+1):0] wr_fifo_sd_addr;
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reg [(LGFIFOLN+1):0] wr_fifo_sd_addr;
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//
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//
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reg [(LGFIFOLN+1):0] ll_fifo_addr;
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reg [(LGFIFOLN+1):0] ll_fifo_addr;
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| Line 523... |
Line 529... |
// Prepare reading of the FIFO for the WB bus read
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// Prepare reading of the FIFO for the WB bus read
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// Memory read #1
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// Memory read #1
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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fifo_a_reg <= {
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fifo_a_reg <= {
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fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
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fifo_a_mem_0[ fifo_wb_addr ],
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fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
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fifo_a_mem_1[ fifo_wb_addr ],
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fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
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fifo_a_mem_2[ fifo_wb_addr ],
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fifo_a_mem[{ fifo_wb_addr, 2'b11 }] };
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fifo_a_mem_3[ fifo_wb_addr ] };
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fifo_b_reg <= {
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fifo_b_reg <= {
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fifo_b_mem[{ fifo_wb_addr, 2'b00 }],
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fifo_b_mem_0[ fifo_wb_addr ],
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fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
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fifo_b_mem_1[ fifo_wb_addr ],
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fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
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fifo_b_mem_2[ fifo_wb_addr ],
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fifo_b_mem[{ fifo_wb_addr, 2'b11 }] };
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fifo_b_mem_3[ fifo_wb_addr ] };
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end
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end
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// Okay, now ... writing our FIFO ...
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// Okay, now ... writing our FIFO ...
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reg pre_fifo_addr_inc_rd;
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reg pre_fifo_addr_inc_rd;
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reg pre_fifo_addr_inc_wr;
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reg pre_fifo_addr_inc_wr;
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| Line 588... |
Line 594... |
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
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pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
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pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
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pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
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clear_fifo_crc <= (cmd_stb)&&(i_wb_data[15]);
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clear_fifo_crc <= (cmd_stb)&&(i_wb_data[15]);
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end
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end
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reg fifo_a_wr, fifo_b_wr;
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reg [3:0] fifo_a_wr_mask, fifo_b_wr_mask;
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reg [(LGFIFOLN-1):0] fifo_a_wr_addr, fifo_b_wr_addr;
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reg [31:0] fifo_a_wr_data, fifo_b_wr_data;
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initial fifo_crc_err = 1'b0;
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initial fifo_crc_err = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin // One and only memory write allowed
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begin // One and only memory write allowed
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fifo_a_wr <= 1'b0;
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fifo_a_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
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if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
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if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
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{fifo_a_mem[{ fifo_wb_addr, 2'b00 }],
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begin
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fifo_a_mem[{ fifo_wb_addr, 2'b01 }],
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fifo_a_wr <= 1'b1;
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fifo_a_mem[{ fifo_wb_addr, 2'b10 }],
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fifo_a_wr_mask <= 4'b1111;
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fifo_a_mem[{ fifo_wb_addr, 2'b11 }] }
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fifo_a_wr_addr <= fifo_wb_addr;
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<= i_wb_data;
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fifo_a_wr_data <= i_wb_data;
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else if (pre_fifo_a_wr)
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end else if (pre_fifo_a_wr)
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fifo_a_mem[{ ll_fifo_addr }] <= ll_out_dat;
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begin
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fifo_a_wr <= 1'b1;
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fifo_a_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
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case(ll_fifo_addr[1:0])
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2'b00: fifo_a_wr_mask <= 4'b0001;
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2'b01: fifo_a_wr_mask <= 4'b0010;
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2'b10: fifo_a_wr_mask <= 4'b0100;
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2'b11: fifo_a_wr_mask <= 4'b1000;
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endcase
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end
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if ((fifo_a_wr)&&(fifo_a_wr_mask[0]))
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fifo_a_mem_0[fifo_a_wr_addr] <= fifo_a_wr_data[7:0];
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if ((fifo_a_wr)&&(fifo_a_wr_mask[1]))
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fifo_a_mem_1[fifo_a_wr_addr] <= fifo_a_wr_data[15:8];
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if ((fifo_a_wr)&&(fifo_a_wr_mask[2]))
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fifo_a_mem_2[fifo_a_wr_addr] <= fifo_a_wr_data[23:16];
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if ((fifo_a_wr)&&(fifo_a_wr_mask[3]))
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fifo_a_mem_3[fifo_a_wr_addr] <= fifo_a_wr_data[31:24];
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fifo_b_wr <= 1'b0;
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fifo_b_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
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if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
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if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
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{fifo_b_mem[{fifo_wb_addr, 2'b00 }],
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begin
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fifo_b_mem[{ fifo_wb_addr, 2'b01 }],
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fifo_b_wr <= 1'b1;
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fifo_b_mem[{ fifo_wb_addr, 2'b10 }],
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fifo_b_wr_mask <= 4'b1111;
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fifo_b_mem[{ fifo_wb_addr, 2'b11 }] }
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fifo_b_wr_addr <= fifo_wb_addr;
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<= i_wb_data;
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fifo_b_wr_data <= i_wb_data;
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else if (pre_fifo_b_wr)
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end else if (pre_fifo_b_wr)
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fifo_b_mem[{ ll_fifo_addr }] <= ll_out_dat;
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begin
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fifo_b_wr <= 1'b1;
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fifo_b_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
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case(ll_fifo_addr[1:0])
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2'b00: fifo_b_wr_mask <= 4'b0001;
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2'b01: fifo_b_wr_mask <= 4'b0010;
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2'b10: fifo_b_wr_mask <= 4'b0100;
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2'b11: fifo_b_wr_mask <= 4'b1000;
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endcase
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end
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if ((fifo_b_wr)&&(fifo_b_wr_mask[0]))
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fifo_b_mem_0[fifo_b_wr_addr] <= fifo_b_wr_data[7:0];
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if ((fifo_b_wr)&&(fifo_b_wr_mask[1]))
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fifo_b_mem_1[fifo_b_wr_addr] <= fifo_b_wr_data[15:8];
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if ((fifo_b_wr)&&(fifo_b_wr_mask[2]))
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fifo_b_mem_2[fifo_b_wr_addr] <= fifo_b_wr_data[23:16];
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if ((fifo_b_wr)&&(fifo_b_wr_mask[3]))
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fifo_b_mem_3[fifo_b_wr_addr] <= fifo_b_wr_data[31:24];
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if (~r_cmd_busy)
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if (~r_cmd_busy)
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ll_fifo_wr_complete <= 1'b0;
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ll_fifo_wr_complete <= 1'b0;
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if (~r_cmd_busy)
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if (~r_cmd_busy)
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| Line 632... |
Line 683... |
fifo_crc_err <= 1'b0;
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fifo_crc_err <= 1'b0;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin // Second memory read, this time for the FIFO
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begin // Second memory read, this time for the FIFO
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fifo_a_byte <= fifo_a_mem[ ll_fifo_addr ];
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case(ll_fifo_addr[1:0])
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fifo_b_byte <= fifo_b_mem[ ll_fifo_addr ];
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2'b00: begin
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fifo_a_byte<=fifo_a_mem_0[ll_fifo_addr[(LGFIFOLN+1):2]];
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fifo_b_byte<=fifo_b_mem_0[ll_fifo_addr[(LGFIFOLN+1):2]];
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end
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2'b01: begin
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fifo_a_byte<=fifo_a_mem_1[ll_fifo_addr[(LGFIFOLN+1):2]];
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fifo_b_byte<=fifo_b_mem_1[ll_fifo_addr[(LGFIFOLN+1):2]];
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end
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2'b10: begin
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fifo_a_byte<=fifo_a_mem_2[ll_fifo_addr[(LGFIFOLN+1):2]];
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fifo_b_byte<=fifo_b_mem_2[ll_fifo_addr[(LGFIFOLN+1):2]];
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end
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2'b11: begin
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fifo_a_byte<=fifo_a_mem_3[ll_fifo_addr[(LGFIFOLN+1):2]];
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fifo_b_byte<=fifo_b_mem_3[ll_fifo_addr[(LGFIFOLN+1):2]];
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end
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endcase
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end
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end
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reg [(LGFIFOLN-1):0] r_blklimit;
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reg [(LGFIFOLN-1):0] r_blklimit;
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wire [(LGFIFOLN+1):0] w_blklimit;
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wire [(LGFIFOLN+1):0] w_blklimit;
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always @(posedge i_clk)
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always @(posedge i_clk)
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