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//
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//
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//
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//
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module spiarbiter(i_clk,
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module spiarbiter(i_clk,
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i_cs_a_n, i_ck_a, i_mosi_a,
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i_cs_a_n, i_ck_a, i_mosi_a,
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i_cs_b_n, i_ck_b, i_mosi_b,
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i_cs_b_n, i_ck_b, i_mosi_b,
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o_cs_a_n, o_cs_b_n, o_ck, o_mosi); // , i_en, o_err
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o_cs_a_n, o_cs_b_n, o_ck, o_mosi,
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o_grant);
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input i_clk;
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input i_clk;
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input i_cs_a_n, i_ck_a, i_mosi_a;
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input i_cs_a_n, i_ck_a, i_mosi_a;
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// output wire o_grant_a;
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// output wire o_grant_a;
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input i_cs_b_n, i_ck_b, i_mosi_b;
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input i_cs_b_n, i_ck_b, i_mosi_b;
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// output wire o_grant_b;
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// output wire o_grant_b;
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output wire o_cs_a_n, o_cs_b_n, o_ck, o_mosi;
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output wire o_cs_a_n, o_cs_b_n, o_ck, o_mosi;
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//
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output wire o_grant; // == o_grant_a = ~o_grant_b
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reg a_owner;
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reg a_owner;
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initial a_owner = 1'b1;
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initial a_owner = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_cs_a_n)&&(i_cs_b_n))
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if ((i_cs_a_n)&&(i_cs_b_n))
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a_owner <= 1'b1; // Keep control
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a_owner <= 1'b1; // Keep control
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else if ((i_cs_a_n)&&(~i_cs_b_n))
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else if ((i_cs_a_n)&&(~i_cs_b_n))
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a_owner <= 1'b0; // Give up control
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a_owner <= 1'b0; // Give up control
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else if ((~i_cs_a_n)&&(i_cs_b_n))
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a_owner <= 1'b1; // Take control
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// assign o_grant_a = a_owner;
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// assign o_grant_a = a_owner;
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// assign o_grant_b = (~a_owner);
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// assign o_grant_b = (~a_owner);
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assign o_cs_a_n = (~a_owner)||(~i_cs_a_n);
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assign o_cs_a_n = (~a_owner)||(i_cs_a_n);
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assign o_cs_b_n = ( a_owner)||(~i_cs_b_n);
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assign o_cs_b_n = ( a_owner)||(i_cs_b_n);
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assign o_ck = ( a_owner)?i_ck_a : i_ck_b;
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assign o_ck = ( a_owner)?i_ck_a : i_ck_b;
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assign o_mosi = ( a_owner)?i_mosi_a : i_mosi_b;
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assign o_mosi = ( a_owner)?i_mosi_a : i_mosi_b;
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assign o_grant = ~a_owner;
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endmodule
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endmodule
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