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Line 41... |
//
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//
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//
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//
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module uartdev(i_clk, i_rx_uart, o_tx_uart,
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module uartdev(i_clk, i_rx_uart, o_tx_uart,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_rx_int, o_tx_int);
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o_rx_int, o_tx_int, o_debug);
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parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 };
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parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 };
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input i_clk, i_rx_uart;
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input i_clk, i_rx_uart;
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output wire o_tx_uart;
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output wire o_tx_uart;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [1:0] i_wb_addr;
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input [1:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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output wire o_rx_int, o_tx_int;
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output wire o_rx_int, o_tx_int;
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output wire [31:0] o_debug;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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reg r_tx_stb, rx_rdy;
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reg r_tx_stb, rx_rdy;
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reg [7:0] r_tx_data;
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reg [7:0] r_tx_data;
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initial r_setup = DEFAULT_SETUP;
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initial r_setup = DEFAULT_SETUP;
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Line 113... |
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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assign o_rx_int = rx_stb;
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assign o_rx_int = rx_stb;
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assign o_tx_int = ~tx_busy;
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assign o_tx_int = ~tx_busy;
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assign o_debug = { (~i_rx_uart)||(~o_tx_uart), tx_busy, i_wb_addr,
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rx_break, rx_frame_err, rx_parity_err, rx_rdy,
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i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack,
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rx_stb, rx_data,
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r_tx_stb, r_tx_data,
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i_rx_uart, o_tx_uart };
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endmodule
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endmodule
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