OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [uartdev.v] - Diff between revs 2 and 7

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 7
Line 2... Line 2...
//
//
// Filename:    uartdev.v
// Filename:    uartdev.v
//
//
// Project:     XuLA2 board
// Project:     XuLA2 board
//
//
// Purpose:     
// Purpose:     This is a simple wrapper around the txuart and rxuart
 
//              modules.  The purpose is to make both of those modules
 
//      configurable from a single wishbone address, and capable of receiving
 
//      (or transmitting) via reads (writes) from two other addresses.
 
//
 
//      It also generates interrupts: a receive interrupt strobe on the clock
 
//      when data is made available, and a transmit not busy level interrupt
 
//      which is held high as long as the transmitter is idle.  Both should be
 
//      able to work nicely with the programmable interrupt controllers found
 
//      in the ZipCPU project.
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.