| Line 80... |
Line 80... |
module wbpwmaudio(i_clk,
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module wbpwmaudio(i_clk,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_pwm, o_int);
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o_pwm, o_int);
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parameter DEFAULT_RELOAD = 16'd1814, // about 44.1 kHz @ 80MHz
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parameter DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @ 80MHz
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//DEFAULT_RELOAD = 16'd2268,//about 44.1 kHz @ 100MHz
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//DEFAULT_RELOAD = 17'd2268,//about 44.1 kHz @ 100MHz
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VARIABLE_RATE=0,
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VARIABLE_RATE=0,
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TIMING_BITS=17;
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TIMING_BITS=17;
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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| Line 112... |
Line 112... |
assign w_reload_value = r_reload_value;
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assign w_reload_value = r_reload_value;
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end else begin
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end else begin
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assign w_reload_value = DEFAULT_RELOAD;
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assign w_reload_value = DEFAULT_RELOAD;
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end endgenerate
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end endgenerate
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reg ztimer;
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reg [(TIMING_BITS-1):0] timer;
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reg [(TIMING_BITS-1):0] timer;
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initial timer = DEFAULT_RELOAD;
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initial timer = DEFAULT_RELOAD;
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initial ztimer= 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (timer == 0)
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ztimer <= (timer == { {(TIMING_BITS-1){1'b0}}, 1'b1 });
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always @(posedge i_clk)
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if (ztimer)
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timer <= w_reload_value;
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timer <= w_reload_value;
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else
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else
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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reg [15:0] sample_out;
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reg [15:0] sample_out;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (timer == 0)
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if (ztimer)
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sample_out <= next_sample;
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sample_out <= next_sample;
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reg [15:0] next_sample;
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reg [15:0] next_sample;
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reg next_valid;
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reg next_valid;
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| Line 138... |
Line 142... |
begin
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begin
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// Write with two's complement data, convert it
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// Write with two's complement data, convert it
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// internally to binary offset
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// internally to binary offset
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_valid <= 1'b1;
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next_valid <= 1'b1;
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end else if (timer == 0)
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end else if (ztimer)
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next_valid <= 1'b0;
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next_valid <= 1'b0;
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_int <= (~next_valid);
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o_int <= (~next_valid);
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