| Line 89... |
Line 89... |
i_wb_addr, i_wb_data,
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i_wb_addr, i_wb_data,
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// Wishbone return values
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// Wishbone return values
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Quad Spi connections to the external device
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// Quad Spi connections to the external device
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o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
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o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
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o_interrupt);
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o_interrupt,
|
|
i_bus_grant);
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parameter AW=18, // Address width, -2 for 32-bit word access
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parameter AW=18, // Address width, -2 for 32-bit word access
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PW=6, // Page address width (256 bytes,64 words)
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PW=6, // Page address width (256 bytes,64 words)
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SW=10; // Sector address width (4kB, 1kW)
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SW=10; // Sector address width (4kB, 1kW)
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// parameter AW, PW, Sw; // Address, page, and sector width(s)
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// parameter AW, PW, Sw; // Address, page, and sector width(s)
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input i_clk_100mhz;
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input i_clk_100mhz;
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| Line 111... |
Line 112... |
input i_spi_cs_n;
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input i_spi_cs_n;
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output wire o_spi_mosi;
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output wire o_spi_mosi;
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input i_spi_miso;
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input i_spi_miso;
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// Interrupt line
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// Interrupt line
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output reg o_interrupt;
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output reg o_interrupt;
|
|
// Do we own the bus?
|
|
input i_bus_grant;
|
|
|
// output wire [31:0] o_debug;
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// output wire [31:0] o_debug;
|
|
|
reg spi_wr, spi_hold;
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reg spi_wr, spi_hold;
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reg [31:0] spi_in;
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reg [31:0] spi_in;
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reg [1:0] spi_len;
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reg [1:0] spi_len;
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| Line 125... |
Line 129... |
// wire [22:0] spi_dbg;
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// wire [22:0] spi_dbg;
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lldspi lldriver(i_clk_100mhz,
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lldspi lldriver(i_clk_100mhz,
|
spi_wr, spi_hold, spi_in, spi_len,
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spi_wr, spi_hold, spi_in, spi_len,
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spi_out, spi_valid, spi_busy,
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spi_out, spi_valid, spi_busy,
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w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
|
w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
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i_spi_miso);
|
i_spi_miso,
|
|
i_bus_grant);
|
|
|
// Erase status tracking
|
// Erase status tracking
|
reg write_in_progress, write_protect;
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reg write_in_progress, write_protect;
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reg [(AW-1-SW):0] erased_sector;
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reg [(AW-1-SW):0] erased_sector;
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reg dirty_sector;
|
reg dirty_sector;
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