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Line 1... |
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbudecompress.v
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// Filename: wbudecompress.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: Compression via this interface is simply a lookup table.
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// Purpose: Compression via this interface is simply a lookup table.
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// When writing, if requested, rather than writing a new 36-bit
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// When writing, if requested, rather than writing a new 36-bit
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// word, we may be asked to repeat a word that's been written recently.
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// word, we may be asked to repeat a word that's been written recently.
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// That's the goal of this routine: if given a word's (relative) address
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// That's the goal of this routine: if given a word's (relative) address
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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reg [9:0] rd_len;
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reg [9:0] rd_len;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~r_word[34])
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if (~r_word[34])
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rd_len <= 10'h01 + { 6'h00, r_word[33:31] };
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rd_len <= 10'h01 + { 6'h00, r_word[33:31] };
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else
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else
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rd_len <= 10'h08 + { 1'b0, r_word[33:31], r_word[29:24] };
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rd_len <= 10'h09 + { 1'b0, r_word[33:31], r_word[29:24] };
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// Clock three, read the table value
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// Clock three, read the table value
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// { o_stb, r_stb } = 4'h4 when done
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// { o_stb, r_stb } = 4'h4 when done
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// Maintaining ...
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// Maintaining ...
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// r_word (clock 1)
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// r_word (clock 1)
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