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[/] [xulalx25soc/] [trunk/] [rtl/] [wbudecompress.v] - Diff between revs 9 and 14

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Rev 9 Rev 14
Line 55... Line 55...
                if ((i_stb)&&(cmd_write_not_compressed))
                if ((i_stb)&&(cmd_write_not_compressed))
                        wr_addr <= wr_addr + 8'h1;
                        wr_addr <= wr_addr + 8'h1;
 
 
        reg     [31:0]   compression_tbl [0:255];
        reg     [31:0]   compression_tbl [0:255];
        always @(posedge i_clk)
        always @(posedge i_clk)
 
                if (i_stb)
                compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
                compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
 
 
        reg     [35:0]   r_word;
        reg     [35:0]   r_word;
        always @(posedge i_clk)
        always @(posedge i_clk)
 
                if (i_stb)
                r_word <= i_word;
                r_word <= i_word;
 
 
 
 
        // Clock two, calculate the table address ... 1 is the smallest address
        // Clock two, calculate the table address ... 1 is the smallest address
        //      { o_stb, r_stb } = 4'h2 when done
        //      { o_stb, r_stb } = 4'h2 when done
Line 125... Line 127...
        // thus ... things will hold still for much longer than just 5 clocks.
        // thus ... things will hold still for much longer than just 5 clocks.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (r_word[35:30] == 6'b101110)
                if (r_word[35:30] == 6'b101110)
                        o_word <= r_word;
                        o_word <= r_word;
                else casez(r_word[35:30])
                else casez(r_word[35:30])
 
                // Set address from something compressed ... unsigned
                6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
                6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
 
                // Set a new address as a signed offset from the last (set) one
 
                //      (The last address is kept further down the chain,
 
                //      we just mark here that the address is to be set
 
                //      relative to it, and by how much.)
                6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0] };
                6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0] };
 
                // Write a value to the bus, with the value given from our
 
                // codeword table
                6'b010???: o_word <=
                6'b010???: o_word <=
                        { 3'h3, cword[31:30], r_word[30], cword[29:0] };
                        { 3'h3, cword[31:30], r_word[30], cword[29:0] };
                6'b10????: o_word <= { 5'b11000, r_word[30],
                // Read, highly compressed length (1 word)
                                20'h00, rd_len };
                6'b10????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
                6'b11????: o_word <= { 5'b11000, r_word[30],
                // Read, two word (3+9 bits) length
                                20'h00, rd_len };
                6'b11????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
                default: o_word <= r_word;
                default: o_word <= r_word;
                endcase
                endcase
endmodule
endmodule
 
 
 
 
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