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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbudeword.v
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// Filename: wbudeword.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: Once a word has come from the bus, undergone compression, had
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// Purpose: Once a word has come from the bus, undergone compression, had
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// idle cycles and interrupts placed in it, this routine converts
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// idle cycles and interrupts placed in it, this routine converts
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// that word form a 36-bit single word into a series of 6-bit words
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// that word form a 36-bit single word into a series of 6-bit words
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// that can head to the output routine. Hence, it 'deword's the value:
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// that can head to the output routine. Hence, it 'deword's the value:
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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