| Line 43... |
Line 43... |
output wire o_err;
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output wire o_err;
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(LGFLEN-1):0] r_first, r_last;
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reg [(LGFLEN-1):0] r_first, r_last;
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wire [(LGFLEN-1):0] nxt_first;
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assign nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
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reg will_overflow;
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reg will_overflow;
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initial will_overflow = 1'b0;
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initial will_overflow = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_overflow <= 1'b0;
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will_overflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_overflow <= (will_overflow)&&(i_wr);
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will_overflow <= (will_overflow)&&(i_wr);
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else if (i_wr)
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else if (i_wr)
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will_overflow <= (r_first+2 == r_last);
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will_overflow <= (r_first+2 == r_last);
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else if (r_first+1 == r_last)
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else if (nxt_first == r_last)
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will_overflow <= 1'b1;
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will_overflow <= 1'b1;
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// Write
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// Write
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initial r_first = 0;
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initial r_first = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_first <= { (LGFLEN){1'b0} };
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r_first <= { (LGFLEN){1'b0} };
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else if (i_wr)
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else if (i_wr)
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begin // Cowardly refuse to overflow
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begin // Cowardly refuse to overflow
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if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
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if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
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r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
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r_first <= nxt_first;
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// else o_ovfl <= 1'b1;
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// else o_ovfl <= 1'b1;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wr) // Write our new value regardless--on overflow or not
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if (i_wr) // Write our new value regardless--on overflow or not
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fifo[r_first] <= i_data;
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fifo[r_first] <= i_data;
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| Line 112... |
Line 115... |
end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
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o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
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:(r_last)];
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:(r_last)];
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wire [(LGFLEN-1):0] nxt_first;
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assign nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
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assign o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
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assign o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
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||((i_rd)&&(will_underflow)&&(~i_wr));
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||((i_rd)&&(will_underflow)&&(~i_wr));
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// wire [(LGFLEN-1):0] fill;
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// wire [(LGFLEN-1):0] fill;
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// assign fill = (r_first-r_last);
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// assign fill = (r_first-r_last);
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