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https://opencores.org/ocsvn/y80e/y80e/trunk
[/] [y80e/] [trunk/] [rtl/] [alu_shft.v] - Diff between revs 2 and 4
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| Rev 2 |
Rev 4 |
| Line 34... |
Line 34... |
`AOP_RLCA: shft_c = alub_in[7];
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`AOP_RLCA: shft_c = alub_in[7];
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`AOP_RR,
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`AOP_RR,
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`AOP_RRA: shft_c = alub_in[0];
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`AOP_RRA: shft_c = alub_in[0];
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`AOP_RRC,
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`AOP_RRC,
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`AOP_RRCA: shft_c = alub_in[0];
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`AOP_RRCA: shft_c = alub_in[0];
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`AOP_SLL,
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`AOP_SLA: shft_c = alub_in[7];
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`AOP_SLA: shft_c = alub_in[7];
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`AOP_SRA: shft_c = alub_in[0];
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`AOP_SRA: shft_c = alub_in[0];
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`AOP_SRL: shft_c = alub_in[0];
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`AOP_SRL: shft_c = alub_in[0];
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default: shft_c = 1'b0;
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default: shft_c = 1'b0;
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endcase
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endcase
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| Line 52... |
Line 53... |
`AOP_RR,
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`AOP_RR,
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`AOP_RRA: shft_out = {carry_bit, alub_in[7:1]};
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`AOP_RRA: shft_out = {carry_bit, alub_in[7:1]};
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`AOP_RRC,
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`AOP_RRC,
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`AOP_RRCA: shft_out = {alub_in[0], alub_in[7:1]};
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`AOP_RRCA: shft_out = {alub_in[0], alub_in[7:1]};
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`AOP_SLA: shft_out = {alub_in[6:0], 1'b0};
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`AOP_SLA: shft_out = {alub_in[6:0], 1'b0};
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`AOP_SLL: shft_out = {alub_in[6:0], 1'b1};
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`AOP_SRA: shft_out = {alub_in[7], alub_in[7:1]};
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`AOP_SRA: shft_out = {alub_in[7], alub_in[7:1]};
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`AOP_SRL: shft_out = {1'b0, alub_in[7:1]};
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`AOP_SRL: shft_out = {1'b0, alub_in[7:1]};
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default: shft_out = 8'h00;
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default: shft_out = 8'h00;
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endcase
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endcase
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end
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end
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