URL https://opencores.org/ocsvn/yac/yac/trunk

Subversion Repositories yac

[/] [yac/] [trunk/] [README.txt] - Diff between revs 6 and 12

Rev 6	Rev 12
Line 79...	Line 79...
`----------------------`	`----------------------`
`- C-model implementation is done`	`- C-model implementation is done`
`- RTL model implementation is done`	`- RTL model implementation is done`
`- RTL model is verified against C-model`	`- RTL model is verified against C-model`
`- Wishbone-bus wrapper is added`	`- Wishbone-bus wrapper is added`
`- included into a small SoC, tested on a spartan-3 FPGA`	`- Included into a small SoC, tested on a spartan-3 FPGA`
	`- Testing within an SOC is done (see ./test_sys)`




`Next-Steps`	`Next-Steps`
`-----------------------`	`-----------------------`
`- Circuit optimizations`	`- Circuit optimizations`
`- Numerical optimizations`	`- Numerical optimizations`
`- Further testing within an SOC`




`=======`	`=======`
Line 112...	Line 112...

`./rtl/vhdl : Contains the VHDL implementation files`	`./rtl/vhdl : Contains the VHDL implementation files`

`./doc : Will contain a detailed documentation in future.`	`./doc : Will contain a detailed documentation in future.`

	`./test_sys : Contains a test system to test the YAC on a spartan-3an board`




`=======`	`=======`