| Line 55... |
Line 55... |
|
|
use work.yavga_pkg.all;
|
use work.yavga_pkg.all;
|
|
|
-- Uncomment the following lines to use the declarations that are
|
-- Uncomment the following lines to use the declarations that are
|
-- provided for instantiating Xilinx primitive components.
|
-- provided for instantiating Xilinx primitive components.
|
library UNISIM;
|
--library UNISIM;
|
use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity chars_RAM is
|
entity chars_RAM is
|
port (
|
port (
|
i_clock_rw : in std_logic; -- Write Clock
|
i_clock_rw : in std_logic; -- Write Clock
|
i_EN_rw : in std_logic; -- Write RAM Enable Input
|
i_EN_rw : in std_logic; -- Write RAM Enable Input
|
| Line 76... |
Line 76... |
i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input
|
i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input
|
o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output
|
o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output
|
);
|
);
|
end chars_RAM;
|
end chars_RAM;
|
|
|
architecture rtl of chars_RAM is
|
architecture Behavioral of chars_RAM is
|
signal s0_DO_r : std_logic_vector(7 downto 0);
|
signal s0_DO_r : std_logic_vector(7 downto 0);
|
signal s1_DO_r : std_logic_vector(7 downto 0);
|
signal s1_DO_r : std_logic_vector(7 downto 0);
|
signal s2_DO_r : std_logic_vector(7 downto 0);
|
signal s2_DO_r : std_logic_vector(7 downto 0);
|
signal s3_DO_r : std_logic_vector(7 downto 0);
|
signal s3_DO_r : std_logic_vector(7 downto 0);
|
|
|
begin
|
constant c_ram_size : natural := 2**(c_CHR_ADDR_BUS_W);
|
|
|
|
type t_ram is array (c_ram_size-1 downto 0) of
|
|
std_logic_vector (c_INTCHR_DATA_BUS_W - 1 downto 0);
|
|
|
u0_chars_ram : RAMB16_S9_S9
|
shared variable v_ram0 : t_ram := (
|
generic map (
|
27 => X"05", -- config "bg and curs color" (108/4 = 27)
|
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1126 => X"53", -- S
|
INIT_A => B"000000000", -- Value of output RAM registers at startup
|
1127 => X"72", -- r
|
SRVAL_A => B"000000000", -- Ouput value upon SSR assertion
|
1128 => X"6D", -- m
|
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1129 => X"20", --
|
INIT_B => B"000000000", -- Value of output RAM registers at startup
|
1130 => X"64", -- d
|
SRVAL_B => B"000000000", -- Ouput value upon SSR assertion
|
1131 => X"6D", -- m
|
--
|
1132 => X"65", -- e
|
INIT_00 => X"000000005E000000000000000000000000000000000000000000000000000000",
|
1133 => X"61", -- a
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
1134 => X"6E", -- n
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
others => X"00"
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"000000000000000000000000000000000000002E636E61736F41640000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
)
|
|
port map(
|
|
-- read
|
|
DIA => (others => '0'), -- 2-bit Data Input
|
|
DIPA => (others => '0'),
|
|
ENA => i_EN_r, -- RAM Enable Input
|
|
WEA => '0', -- Write Enable Input
|
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKA => i_clock_r, -- Clock
|
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
|
DOA => s0_DO_r, -- 8-bit Data Output
|
|
DOPA => open,
|
|
|
|
-- read/write
|
|
DIB => i_DI_rw(7 downto 0), -- 8-bit Data Input
|
|
DIPB => (others => '0'),
|
|
ENB => i_EN_rw, -- RAM Enable Input
|
|
WEB => i_WE_rw(0), -- Write Enable Input
|
|
SSRB => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKB => i_clock_rw, -- Clock
|
|
ADDRB => i_ADDR_rw, -- 11-bit Address Input
|
|
DOB => o_DI_rw(7 downto 0), -- 8-bit Data Input
|
|
DOPB => open
|
|
);
|
);
|
|
|
u1_chars_ram : RAMB16_S9_S9
|
shared variable v_ram1 : t_ram := (
|
generic map (
|
27 => X"07", -- config "xy coords spans on three bytes" (108/4 = 27)
|
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1126 => X"61", -- a
|
INIT_A => B"000000000", -- Value of output RAM registers at startup
|
1127 => X"6F", -- o
|
SRVAL_A => B"000000000", -- Ouput value upon SSR assertion
|
1128 => X"61", -- a
|
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1129 => X"2D", -- -
|
INIT_B => B"000000000", -- Value of output RAM registers at startup
|
1130 => X"72", -- r
|
SRVAL_B => B"000000000", -- Ouput value upon SSR assertion
|
1131 => X"74", -- t
|
--
|
1132 => X"74", -- t
|
INIT_00 => X"0000000009000000000000000000000000000000000000000000000000000000",
|
1133 => X"70", -- p
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
1134 => X"65", -- e
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
others => X"00"
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"000000000000000000000000000000000000746573406F2074206E0000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
)
|
|
port map(
|
|
-- read
|
|
DIA => (others => '0'), -- 2-bit Data Input
|
|
DIPA => (others => '0'),
|
|
ENA => i_EN_r, -- RAM Enable Input
|
|
WEA => '0', -- Write Enable Input
|
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKA => i_clock_r, -- Clock
|
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
|
DOA => s1_DO_r, -- 8-bit Data Output
|
|
DOPA => open,
|
|
|
|
-- read/write
|
|
DIB => i_DI_rw(15 downto 8), -- 8-bit Data Input
|
|
DIPB => (others => '0'),
|
|
ENB => i_EN_rw, -- RAM Enable Input
|
|
WEB => i_WE_rw(1), -- Write Enable Input
|
|
SSRB => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKB => i_clock_rw, -- Clock
|
|
ADDRB => i_ADDR_rw, -- 11-bit Address Input
|
|
DOB => o_DI_rw(15 downto 8), -- 8-bit Data Input
|
|
DOPB => open
|
|
);
|
);
|
|
|
u2_chars_ram : RAMB16_S9_S9
|
shared variable v_ram2 : t_ram := (
|
generic map (
|
27 => X"09", -- config "xy coords spans on three bytes" (108/4 = 27)
|
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1126 => X"6E", -- n
|
INIT_A => B"000000000", -- Value of output RAM registers at startup
|
1127 => X"20", --
|
SRVAL_A => B"000000000", -- Ouput value upon SSR assertion
|
1128 => X"74", -- t
|
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1129 => X"20", --
|
INIT_B => B"000000000", -- Value of output RAM registers at startup
|
1130 => X"6F", -- o
|
SRVAL_B => B"000000000", -- Ouput value upon SSR assertion
|
1131 => X"40", -- @
|
--
|
1132 => X"73", -- s
|
INIT_00 => X"0000000007000000000000000000000000000000000000000000000000000000",
|
1133 => X"65", -- e
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
1134 => X"74", -- t
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
others => X"00"
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"00000000000000000000000000000000000065707474722D616F610000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
)
|
|
port map(
|
|
-- read
|
|
DIA => (others => '0'), -- 2-bit Data Input
|
|
DIPA => (others => '0'),
|
|
ENA => i_EN_r, -- RAM Enable Input
|
|
WEA => '0', -- Write Enable Input
|
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKA => i_clock_r, -- Clock
|
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
|
DOA => s2_DO_r, -- 8-bit Data Output
|
|
DOPA => open,
|
|
|
|
-- read/write
|
|
DIB => i_DI_rw(23 downto 16), -- 8-bit Data Input
|
|
DIPB => (others => '0'),
|
|
ENB => i_EN_rw, -- RAM Enable Input
|
|
WEB => i_WE_rw(2), -- Write Enable Input
|
|
SSRB => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKB => i_clock_rw, -- Clock
|
|
ADDRB => i_ADDR_rw, -- 11-bit Address Input
|
|
DOB => o_DI_rw(23 downto 16), -- 8-bit Data Input
|
|
DOPB => open
|
|
);
|
);
|
|
|
u3_chars_ram : RAMB16_S9_S9
|
shared variable v_ram3 : t_ram := (
|
generic map (
|
27 => X"5E", -- config "xy coords spans on three bytes" (108/4 = 27)
|
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1126 => X"64", -- d
|
INIT_A => B"000000000", -- Value of output RAM registers at startup
|
1127 => X"41", -- A
|
SRVAL_A => B"000000000", -- Ouput value upon SSR assertion
|
1128 => X"6F", -- o
|
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
1129 => X"73", -- s
|
INIT_B => B"000000000", -- Value of output RAM registers at startup
|
1130 => X"61", -- a
|
SRVAL_B => B"000000000", -- Ouput value upon SSR assertion
|
1131 => X"6E", -- n
|
--
|
1132 => X"63", -- c
|
INIT_00 => X"0000000005000000000000000000000000000000000000000000000000000000",
|
1133 => X"2E", -- .
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
1134 => X"20", --
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
others => X"00"
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"0000000000000000000000000000000000006E61656D64206D72530000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
|
|
)
|
|
port map(
|
|
-- read
|
|
DIA => (others => '0'), -- 2-bit Data Input
|
|
DIPA => (others => '0'),
|
|
ENA => i_EN_r, -- RAM Enable Input
|
|
WEA => '0', -- Write Enable Input
|
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKA => i_clock_r, -- Clock
|
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
|
DOA => s3_DO_r, -- 8-bit Data Output
|
|
DOPA => open,
|
|
|
|
-- read/write
|
|
DIB => i_DI_rw(31 downto 24), -- 8-bit Data Input
|
|
DIPB => (others => '0'),
|
|
ENB => i_EN_rw, -- RAM Enable Input
|
|
WEB => i_WE_rw(3), -- Write Enable Input
|
|
SSRB => i_SSR, -- Synchronous Set/Reset Input
|
|
CLKB => i_clock_rw, -- Clock
|
|
ADDRB => i_ADDR_rw, -- 11-bit Address Input
|
|
DOB => o_DI_rw(31 downto 24), -- 8-bit Data Input
|
|
DOPB => open
|
|
);
|
);
|
|
|
o_DO_r <= s0_DO_r when i_ADDR_r(1 downto 0) = "11" else
|
begin
|
s1_DO_r when i_ADDR_r(1 downto 0) = "10" else
|
|
s2_DO_r when i_ADDR_r(1 downto 0) = "01" else
|
p_rw0_port : process (i_clock_rw)
|
s3_DO_r when i_ADDR_r(1 downto 0) = "00" else
|
begin
|
(others => 'X');
|
if rising_edge(i_clock_rw) then
|
|
if i_SSR = '1' then
|
|
o_DI_rw(31 downto 24) <= (others => '0');
|
|
elsif (i_EN_rw = '1') then
|
|
o_DI_rw(31 downto 24) <= v_ram0(conv_integer(i_ADDR_rw));
|
|
if (i_WE_rw(0) = '1') then
|
|
v_ram0(conv_integer(i_ADDR_rw)) := i_DI_rw(31 downto 24);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
end rtl;
|
p_rw1_port : process (i_clock_rw)
|
|
begin
|
|
if rising_edge(i_clock_rw) then
|
|
if i_SSR = '1' then
|
|
o_DI_rw(23 downto 16) <= (others => '0');
|
|
elsif (i_EN_rw = '1') then
|
|
o_DI_rw(23 downto 16) <= v_ram1(conv_integer(i_ADDR_rw));
|
|
if (i_WE_rw(1) = '1') then
|
|
v_ram1(conv_integer(i_ADDR_rw)) := i_DI_rw(23 downto 16);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_rw2_port : process (i_clock_rw)
|
|
begin
|
|
if rising_edge(i_clock_rw) then
|
|
if i_SSR = '1' then
|
|
o_DI_rw(15 downto 8) <= (others => '0');
|
|
elsif (i_EN_rw = '1') then
|
|
o_DI_rw(15 downto 8) <= v_ram2(conv_integer(i_ADDR_rw));
|
|
if (i_WE_rw(2) = '1') then
|
|
v_ram2(conv_integer(i_ADDR_rw)) := i_DI_rw(15 downto 8);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_rw3_port : process (i_clock_rw)
|
|
begin
|
|
if rising_edge(i_clock_rw) then
|
|
if i_SSR = '1' then
|
|
o_DI_rw(7 downto 0) <= (others => '0');
|
|
elsif (i_EN_rw = '1') then
|
|
o_DI_rw(7 downto 0) <= v_ram3(conv_integer(i_ADDR_rw));
|
|
if (i_WE_rw(3) = '1') then
|
|
v_ram3(conv_integer(i_ADDR_rw)) := i_DI_rw(7 downto 0);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
p_ro0_port : process (i_clock_r)
|
|
begin
|
|
if rising_edge(i_clock_r) then
|
|
if i_SSR = '1' then
|
|
s0_DO_r <= (others => '0');
|
|
elsif (i_EN_r = '1') then
|
|
s0_DO_r <= v_ram0(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_ro1_port : process (i_clock_r)
|
|
begin
|
|
if rising_edge(i_clock_r) then
|
|
if i_SSR = '1' then
|
|
s1_DO_r <= (others => '0');
|
|
elsif (i_EN_r = '1') then
|
|
s1_DO_r <= v_ram1(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_ro2_port : process (i_clock_r)
|
|
begin
|
|
if rising_edge(i_clock_r) then
|
|
if i_SSR = '1' then
|
|
s2_DO_r <= (others => '0');
|
|
elsif (i_EN_r = '1') then
|
|
s2_DO_r <= v_ram2(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_ro3_port : process (i_clock_r)
|
|
begin
|
|
if rising_edge(i_clock_r) then
|
|
if i_SSR = '1' then
|
|
s3_DO_r <= (others => '0');
|
|
elsif (i_EN_r = '1') then
|
|
s3_DO_r <= v_ram3(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
o_DO_r <=
|
|
s0_DO_r when i_ADDR_r(1 downto 0) = "00" else
|
|
s1_DO_r when i_ADDR_r(1 downto 0) = "01" else
|
|
s2_DO_r when i_ADDR_r(1 downto 0) = "10" else
|
|
s3_DO_r when i_ADDR_r(1 downto 0) = "11" else
|
|
(others => 'X');
|
|
end Behavioral;
|
|
|
No newline at end of file
|
No newline at end of file
|
