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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [wb_port/] [wb_port_tb.v] - Diff between revs 2 and 22

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Rev 2	Rev 22
Line 45...	Line 45...

`initial begin`	`initial begin`
`clock = 0;`	`clock = 0;`
`end`	`end`

	`ifdef WFDUMP
`initial begin`	`initial begin`
`$dumpfile("wb_port.vcd");`	`$dumpfile("wb_port.vcd");`
`$dumpvars(0, wb_port_tb);`	`$dumpvars(0, wb_port_tb.uut.mprj);`
	`end`
	`endif

	`initial begin`

`// Repeat cycles of 1000 clock edges as needed to complete testbench`	`// Repeat cycles of 1000 clock edges as needed to complete testbench`
`repeat (30) begin`	`repeat (30) begin`
`repeat (1000) @(posedge clock);`	`repeat (1000) @(posedge clock);`
`// $display("+1000 cycles");`	`// $display("+1000 cycles");`
`end`	`end`
`$display("%c[1;31m",27);`	`$display("%c[1;31m",27);`
	`$display ("##########################################################");`
`ifdef GL	`ifdef GL
`$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");`	`$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");`
`else	`else
`$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");`	`$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");`
`endif	`endif
	`$display ("##########################################################");`
`$display("%c[0m",27);`	`$display("%c[0m",27);`
`$finish;`	`$finish;`
`end`	`end`

`initial begin`	`initial begin`
`wait(checkbits == 16'h AB60);`	`wait(checkbits == 16'h AB60);`
`$display("Monitor: MPRJ-Logic WB Started");`	`$display("Monitor: MPRJ-Logic WB Started");`
`wait(checkbits == 16'h AB61);`	`wait(checkbits == 16'h AB61);`
	`$display ("##########################################################");`
`ifdef GL	`ifdef GL
`$display("Monitor: Mega-Project WB (GL) Passed");`	`$display("Monitor: Mega-Project WB (GL) Passed");`
`else	`else
`$display("Monitor: Mega-Project WB (RTL) Passed");`	`$display("Monitor: Mega-Project WB (RTL) Passed");`
`endif	`endif
	`$display ("##########################################################");`
`$finish;`	`$finish;`
`end`	`end`

`initial begin`	`initial begin`
`RSTB <= 1'b0;`	`RSTB <= 1'b0;`
Line 100...	Line 109...
`power3 <= 1'b1;`	`power3 <= 1'b1;`
`#100;`	`#100;`
`power4 <= 1'b1;`	`power4 <= 1'b1;`
`end`	`end`

`always @(mprj_io) begin`	`//always @(mprj_io) begin`
`#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);`	`// #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);`
`end`	`//end`

`wire flash_csb;`	`wire flash_csb;`
`wire flash_clk;`	`wire flash_clk;`
`wire flash_io0;`	`wire flash_io0;`
`wire flash_io1;`	`wire flash_io1;`
Line 153...	Line 162...
`.io3() // not used`	`.io3() // not used`
`);`	`);`

`endmodule`	`endmodule`
`default_nettype wire	`default_nettype wire
`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [wb_port/] [wb_port_tb.v] - Diff between revs 2 and 22