| Line 62... |
Line 62... |
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reg [DATA_WIDTH-1:0] ram [FIFO_DEPTH-1:0];
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reg [DATA_WIDTH-1:0] ram [FIFO_DEPTH-1:0];
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reg [ADDR_WIDTH-1:0] wptr; // write ptr
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reg [ADDR_WIDTH-1:0] wptr; // write ptr
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reg [ADDR_WIDTH-1:0] rptr; // write ptr
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reg [ADDR_WIDTH-1:0] rptr; // write ptr
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reg [ADDR_WIDTH:0] status_cnt; // status counter
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reg [ADDR_WIDTH:0] status_cnt; // status counter
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reg empty;
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reg full;
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//-----------Variable assignments---------------
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assign full = (status_cnt == FIFO_DEPTH);
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assign empty = (status_cnt == 0);
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//-----------Code Start---------------------------
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//-----------Code Start---------------------------
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always @ (negedge rstn or posedge clk)
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always @ (negedge rstn or posedge clk)
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begin : WRITE_POINTER
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begin : WRITE_POINTER
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if (rstn==1'b0) begin
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if (rstn==1'b0) begin
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| Line 99... |
Line 98... |
end else if (wr_en && (!rd_en) && (status_cnt != FIFO_DEPTH)) begin
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end else if (wr_en && (!rd_en) && (status_cnt != FIFO_DEPTH)) begin
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status_cnt <= status_cnt + 1;
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status_cnt <= status_cnt + 1;
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end
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end
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end
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end
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// underflow is not handled
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always @ (negedge rstn or posedge clk)
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begin : EMPTY_FLAG
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if (rstn==1'b0) begin
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empty <= 1;
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// Read but no write.
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end else if (rd_en && (!wr_en) && (status_cnt == 1)) begin
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empty <= 1;
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// Write
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end else if (wr_en) begin
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empty <= 0;
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end else if (status_cnt == 0) begin
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empty <= 1;
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end
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end
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// overflow is not handled
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always @ (negedge rstn or posedge clk)
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begin : FULL_FLAG
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if (rstn==1'b0) begin
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full <= 0;
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// Write but no read.
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end else if (wr_en && (!rd_en) && (status_cnt == (FIFO_DEPTH-1))) begin
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full <= 1;
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// Read
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end else if (rd_en && (!wr_en) ) begin
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full <= 0;
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end else if (status_cnt == FIFO_DEPTH) begin
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full <= 1;
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end
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end
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assign dout = ram[rptr];
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assign dout = ram[rptr];
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (wr_en) ram[wptr] <= din;
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if (wr_en) ram[wptr] <= din;
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