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//////////////////////////////////////////////////////////////////////
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/*********************************************************************
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//// ////
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//// YiFive cores common library Module ////
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This file is part of the sdram controller project
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//// ////
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http://www.opencores.org/cores/sdr_ctrl/
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//// This file is part of the YIFive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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Description: SYNC FIFO
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//// ////
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Parameters:
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//// Description ////
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W : Width (integer)
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//// Sync Fifo with full and empty ////
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D : Depth (integer, power of 2, 4 to 256)
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//// ////
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//// To Do: ////
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To Do:
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//// nothing ////
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nothing
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//// ////
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//// Author(s): ////
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Author(s): Dinesh Annayya, dinesha@opencores.org
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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Copyright (C) 2000 Authors and OPENCORES.ORG
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//// Revision : June 7, 2021 ////
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//// ////
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This source file may be used and distributed without
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//////////////////////////////////////////////////////////////////////
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restriction provided that this copyright statement is not
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//// ////
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removed from the file and that any derivative work contains
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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the original copyright notice and the associated disclaimer.
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//// ////
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//// This source file may be used and distributed without ////
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This source file is free software; you can redistribute it
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//// restriction provided that this copyright statement is not ////
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and/or modify it under the terms of the GNU Lesser General
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//// removed from the file and that any derivative work contains ////
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Public License as published by the Free Software Foundation;
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//// the original copyright notice and the associated disclaimer. ////
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either version 2.1 of the License, or (at your option) any
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//// ////
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later version.
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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This source is distributed in the hope that it will be
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//// Public License as published by the Free Software Foundation; ////
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useful, but WITHOUT ANY WARRANTY; without even the implied
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//// either version 2.1 of the License, or (at your option) any ////
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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//// later version. ////
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PURPOSE. See the GNU Lesser General Public License for more
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//// ////
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details.
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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You should have received a copy of the GNU Lesser General
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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Public License along with this source; if not, download it
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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from http://www.opencores.org/lgpl.shtml
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//// details. ////
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//// ////
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*******************************************************************/
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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module sync_fifo (clk,
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//// ////
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reset_n,
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//////////////////////////////////////////////////////////////////////
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wr_en,
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wr_data,
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module sync_fifo #(
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full,
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parameter DATA_WIDTH = 32, // Data Width
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empty,
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parameter ADDR_WIDTH = 1, // Address Width
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rd_en,
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parameter FIFO_DEPTH = 2 // FIFO DEPTH
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rd_data);
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)(
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parameter W = 8;
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output [DATA_WIDTH-1:0] dout,
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parameter D = 4;
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input rstn,
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input clk,
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parameter AW = (D == 4) ? 2 :
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input wr_en, // Write
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(D == 8) ? 3 :
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input rd_en, // Read
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(D == 16) ? 4 :
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input [DATA_WIDTH-1:0] din,
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(D == 32) ? 5 :
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output full,
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(D == 64) ? 6 :
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output empty
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(D == 128) ? 7 :
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);
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(D == 256) ? 8 : 0;
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output [W-1 : 0] rd_data;
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reg [DATA_WIDTH-1:0] ram [FIFO_DEPTH-1:0];
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input [W-1 : 0] wr_data;
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reg [ADDR_WIDTH-1:0] wptr; // write ptr
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input clk, reset_n, wr_en, rd_en;
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reg [ADDR_WIDTH-1:0] rptr; // write ptr
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output full, empty;
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reg [ADDR_WIDTH:0] status_cnt; // status counter
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reg empty;
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// synopsys translate_off
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reg full;
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initial begin
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if (AW == 0) begin
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//-----------Code Start---------------------------
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$display ("%m : ERROR!!! Fifo depth %d not in range 4 to 256", D);
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always @ (negedge rstn or posedge clk)
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end // if (AW == 0)
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begin : WRITE_POINTER
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end // initial begin
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if (rstn==1'b0) begin
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wptr <= 0;
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// synopsys translate_on
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end else if (wr_en ) begin
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wptr <= wptr + 1;
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end
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reg [W-1 : 0] mem[D-1 : 0];
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end
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reg [AW-1 : 0] rd_ptr, wr_ptr;
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reg full, empty;
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always @ (negedge rstn or posedge clk)
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begin : READ_POINTER
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wire [W-1 : 0] rd_data;
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if (rstn==1'b0) begin
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rptr <= 0;
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always @ (posedge clk or negedge reset_n)
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end else if (rd_en) begin
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if (reset_n == 1'b0) begin
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rptr <= rptr + 1;
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wr_ptr <= {AW{1'b0}} ;
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end
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end
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always @ (negedge rstn or posedge clk)
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begin : STATUS_COUNTER
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if (rstn==1'b0) begin
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status_cnt <= 0;
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// Read but no write.
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end else if (rd_en && (!wr_en) && (status_cnt != 0)) begin
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status_cnt <= status_cnt - 1;
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// Write but no read.
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end else if (wr_en && (!rd_en) && (status_cnt != FIFO_DEPTH)) begin
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status_cnt <= status_cnt + 1;
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end
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end
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// underflow is not handled
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always @ (negedge rstn or posedge clk)
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begin : EMPTY_FLAG
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if (rstn==1'b0) begin
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empty <= 1;
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// Read but no write.
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end else if (rd_en && (!wr_en) && (status_cnt == 1)) begin
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empty <= 1;
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// Write
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end else if (wr_en) begin
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empty <= 0;
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end else if (status_cnt == 0) begin
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empty <= 1;
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end
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end
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// overflow is not handled
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always @ (negedge rstn or posedge clk)
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begin : FULL_FLAG
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if (rstn==1'b0) begin
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full <= 0;
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// Write but no read.
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end else if (wr_en && (!rd_en) && (status_cnt == (FIFO_DEPTH-1))) begin
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full <= 1;
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// Read
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end else if (rd_en && (!wr_en) ) begin
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full <= 0;
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end else if (status_cnt == FIFO_DEPTH) begin
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full <= 1;
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end
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end
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else begin
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if (wr_en & !full) begin
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wr_ptr <= wr_ptr + 1'b1 ;
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end
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end
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always @ (posedge clk or negedge reset_n)
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if (reset_n == 1'b0) begin
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rd_ptr <= {AW{1'b0}} ;
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end
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else begin
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if (rd_en & !empty) begin
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rd_ptr <= rd_ptr + 1'b1 ;
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end
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end
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always @ (posedge clk or negedge reset_n)
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if (reset_n == 1'b0) begin
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empty <= 1'b1 ;
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end
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else begin
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empty <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b0}}, 1'b1}) & rd_en & ~wr_en) ? 1'b1 :
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((wr_ptr == rd_ptr) & ~rd_en & wr_en) ? 1'b0 : empty ;
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end
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always @ (posedge clk or negedge reset_n)
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if (reset_n == 1'b0) begin
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full <= 1'b0 ;
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end
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else begin
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full <= (((wr_ptr - rd_ptr) == {{(AW-1){1'b1}}, 1'b0}) & ~rd_en & wr_en) ? 1'b1 :
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(((wr_ptr - rd_ptr) == {AW{1'b1}}) & rd_en & ~wr_en) ? 1'b0 : full ;
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end
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end
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assign dout = ram[rptr];
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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if (wr_en)
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if (wr_en) ram[wptr] <= din;
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mem[wr_ptr] <= wr_data;
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assign rd_data = mem[rd_ptr];
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// synopsys translate_off
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always @(posedge clk) begin
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if (wr_en && full) begin
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$display("%m : Error! sfifo overflow!");
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end
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end
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end
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always @(posedge clk) begin
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if (rd_en && empty) begin
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$display("%m : error! sfifo underflow!");
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end
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end
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// synopsys translate_on
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//---------------------------------------
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endmodule
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endmodule
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