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https://opencores.org/ocsvn/yifive/yifive/trunk
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| Rev 18 |
Rev 21 |
| Line 83... |
Line 83... |
if(en)
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if(en)
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begin
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begin
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if(clk_cnt == sck_half_period)
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if(clk_cnt == sck_half_period)
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begin
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begin
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spi_clk <= 1'b0;
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spi_clk <= 1'b0;
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spi_fall <= 1'b1;
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end // if (clk_cnt == sck_half_period)
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else if(clk_cnt == cfg_sck_period) begin
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spi_clk <= 1'b1;
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end
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end else begin
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spi_clk <= 1'b1;
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end // else: !if(en)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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// Generate Free runnng spi_fall and rise pulse
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// after en is asserted
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always @(posedge clk or negedge rstn) begin
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if(!rstn) begin
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clk_cnt <= 'h1;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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spi_rise <= 1'b0;
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end // if (!reset_n)
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else
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begin
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if(clk_cnt == sck_half_period)
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begin
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spi_fall <= 1'b0;
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spi_rise <= 1'b1;
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clk_cnt <= clk_cnt + 1'b1;
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clk_cnt <= clk_cnt + 1'b1;
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end // if (clk_cnt == sck_half_period)
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end // if (clk_cnt == sck_half_period)
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else begin
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else begin
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if(clk_cnt == cfg_sck_period)
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if(clk_cnt == cfg_sck_period)
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begin
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begin
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spi_clk <= 1'b1;
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spi_fall <= 1'b1;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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spi_rise <= 1'b1;
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clk_cnt <= 'h1;
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clk_cnt <= 'h1;
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end // if (clk_cnt == cfg_sck_period)
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end // if (clk_cnt == cfg_sck_period)
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else
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else
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begin
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begin
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clk_cnt <= clk_cnt + 1'b1;
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clk_cnt <= clk_cnt + 1'b1;
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spi_fall <= 1'b0;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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spi_rise <= 1'b0;
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end // else: !if(clk_cnt == cfg_sck_period)
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end // else: !if(clk_cnt == cfg_sck_period)
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end // else: !if(clk_cnt == sck_half_period)
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end // else: !if(clk_cnt == sck_half_period)
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end // if (en)
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else begin
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clk_cnt <= 'h1;
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spi_fall <= 1'b0;
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spi_rise <= 1'b0;
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end // else: !if(en)
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end // else: !if(!reset_n)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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end // always @ (posedge clk or negedge reset_n)
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endmodule
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endmodule
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