| Line 49... |
Line 49... |
input logic rstn,
|
input logic rstn,
|
output logic eot,
|
output logic eot,
|
|
|
input logic [7:0] spi_clk_div,
|
input logic [7:0] spi_clk_div,
|
input logic spi_clk_div_valid,
|
input logic spi_clk_div_valid,
|
output logic [7:0] spi_status,
|
output logic [8:0] spi_status,
|
|
|
|
|
input logic spi_req,
|
input logic spi_req,
|
input logic [31:0] spi_addr,
|
input logic [31:0] spi_addr,
|
input logic [5:0] spi_addr_len,
|
input logic [5:0] spi_addr_len,
|
| Line 131... |
Line 131... |
logic en_quad_in;
|
logic en_quad_in;
|
|
|
|
|
enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;
|
enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;
|
|
|
enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;
|
enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY_RX,DUMMY_TX,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;
|
|
|
assign en_quad = spi_qrd | spi_qwr | en_quad_int;
|
assign en_quad = spi_qrd | spi_qwr | en_quad_int;
|
|
|
|
|
assign en_quad_in = (s_spi_mode == SPI_STD) ? 1'b0 : 1'b1;
|
assign en_quad_in = (s_spi_mode == SPI_STD) ? 1'b0 : 1'b1;
|
| Line 167... |
Line 167... |
.txdata ( data_to_tx ),
|
.txdata ( data_to_tx ),
|
.data_valid ( data_to_tx_valid ),
|
.data_valid ( data_to_tx_valid ),
|
.data_ready ( ),
|
.data_ready ( ),
|
.clk_en_o ( tx_clk_en )
|
.clk_en_o ( tx_clk_en )
|
);
|
);
|
|
|
spim_rx u_rxreg
|
spim_rx u_rxreg
|
(
|
(
|
.clk ( clk ),
|
.clk ( clk ),
|
.rstn ( rstn ),
|
.rstn ( rstn ),
|
.en ( spi_en_rx ),
|
.en ( spi_en_rx ),
|
| Line 189... |
Line 188... |
.data_ready ( 1'b1 ),
|
.data_ready ( 1'b1 ),
|
.clk_en_o ( rx_clk_en )
|
.clk_en_o ( rx_clk_en )
|
);
|
);
|
|
|
|
|
|
|
always_comb
|
always_comb
|
begin
|
begin
|
data_to_tx = 'h0;
|
data_to_tx = 'h0;
|
data_to_tx_valid = 1'b0;
|
data_to_tx_valid = 1'b0;
|
|
|
| Line 254... |
Line 252... |
case(state)
|
case(state)
|
IDLE:
|
IDLE:
|
begin
|
begin
|
spi_status[0] = 1'b1;
|
spi_status[0] = 1'b1;
|
s_spi_mode = SPI_QUAD_RX;
|
s_spi_mode = SPI_QUAD_RX;
|
if (spi_req)
|
if (spi_req && spi_fall)
|
begin
|
begin
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = 1'b1;
|
spi_clock_en = 1'b1;
|
|
|
if (spi_cmd_len != 0)
|
if (spi_cmd_len != 0)
|
| Line 297... |
Line 295... |
if (spi_rd || spi_qrd)
|
if (spi_rd || spi_qrd)
|
begin
|
begin
|
s_spi_mode = (spi_qrd) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (spi_qrd) ? SPI_QUAD_RX : SPI_STD;
|
if(spi_dummy_rd_len != 0)
|
if(spi_dummy_rd_len != 0)
|
begin
|
begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_tx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_en_rx = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
state_next = DUMMY;
|
spi_clock_en = rx_clk_en;
|
|
state_next = DUMMY_RX;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_rx = spi_data_len;
|
counter_rx = spi_data_len;
|
counter_rx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_rx = 1'b1;
|
spi_en_rx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
state_next = DATA_RX;
|
state_next = DATA_RX;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 320... |
Line 320... |
begin
|
begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
state_next = DUMMY;
|
spi_clock_en = tx_clk_en;
|
|
state_next = DUMMY_TX;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_tx = spi_data_len;
|
counter_tx = spi_data_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_valid = 1'b0;
|
ctrl_data_valid = 1'b0;
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
|
spi_clock_en = tx_clk_en;
|
state_next = DATA_TX;
|
state_next = DATA_TX;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 348... |
Line 350... |
spi_status[1] = 1'b1;
|
spi_status[1] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = 1'b1;
|
spi_clock_en = 1'b1;
|
// s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
// s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = SPI_STD; // Command is always Standard Mode ?
|
s_spi_mode = SPI_STD; // Command is always Standard Mode ?
|
if (tx_done)
|
if (tx_done && spi_fall)
|
begin
|
begin
|
if (spi_addr_len != 0)
|
if (spi_addr_len != 0)
|
begin
|
begin
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
counter_tx = {8'h0,spi_addr_len};
|
counter_tx = {8'h0,spi_addr_len};
|
| Line 377... |
Line 379... |
if (do_rx)
|
if (do_rx)
|
begin
|
begin
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
if(spi_dummy_rd_len != 0)
|
if(spi_dummy_rd_len != 0)
|
begin
|
begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_tx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_en_rx = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
state_next = DUMMY;
|
spi_clock_en = rx_clk_en;
|
|
state_next = DUMMY_RX;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_rx = spi_data_len;
|
counter_rx = spi_data_len;
|
counter_rx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_rx = 1'b1;
|
spi_en_rx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
state_next = DATA_RX;
|
state_next = DATA_RX;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 400... |
Line 404... |
begin
|
begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
state_next = DUMMY;
|
spi_clock_en = tx_clk_en;
|
|
state_next = DUMMY_TX;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_tx = spi_data_len;
|
counter_tx = spi_data_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_valid = 1'b1;
|
ctrl_data_valid = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
|
spi_clock_en = tx_clk_en;
|
state_next = DATA_TX;
|
state_next = DATA_TX;
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
else
|
| Line 434... |
Line 440... |
spi_status[2] = 1'b1;
|
spi_status[2] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = 1'b1;
|
spi_clock_en = 1'b1;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
|
|
if (tx_done)
|
if (tx_done && spi_fall)
|
begin
|
begin
|
if (spi_mode_cmd_enb != 0)
|
if (spi_mode_cmd_enb != 0)
|
begin
|
begin
|
s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
|
counter_tx = {8'h0,8'h8};
|
counter_tx = {8'h0,8'h8};
|
| Line 453... |
Line 459... |
if (do_rx)
|
if (do_rx)
|
begin
|
begin
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
if(spi_dummy_rd_len != 0)
|
if(spi_dummy_rd_len != 0)
|
begin
|
begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_tx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_en_rx = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
state_next = DUMMY;
|
spi_clock_en = rx_clk_en;
|
|
state_next = DUMMY_RX;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_rx = spi_data_len;
|
counter_rx = spi_data_len;
|
counter_rx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_rx = 1'b1;
|
spi_en_rx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
state_next = DATA_RX;
|
state_next = DATA_RX;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 476... |
Line 484... |
|
|
if(spi_dummy_wr_len != 0) begin
|
if(spi_dummy_wr_len != 0) begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
state_next = DUMMY;
|
spi_clock_en = tx_clk_en;
|
|
state_next = DUMMY_TX;
|
end else begin
|
end else begin
|
counter_tx = spi_data_len;
|
counter_tx = spi_data_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_valid = 1'b1;
|
ctrl_data_valid = 1'b1;
|
|
spi_clock_en = tx_clk_en;
|
state_next = DATA_TX;
|
state_next = DATA_TX;
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
else
|
| Line 500... |
Line 510... |
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_status[3] = 1'b1;
|
spi_status[3] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = 1'b1;
|
spi_clock_en = 1'b1;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
if (tx_done)
|
if (tx_done && spi_fall)
|
begin
|
begin
|
if (spi_data_len != 0)
|
if (spi_data_len != 0)
|
begin
|
begin
|
if (do_rx)
|
if (do_rx)
|
begin
|
begin
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
if(spi_dummy_rd_len != 0)
|
if(spi_dummy_rd_len != 0)
|
begin
|
begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_rx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
|
counter_tx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_en_rx = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
state_next = DUMMY;
|
spi_clock_en = rx_clk_en;
|
|
state_next = DUMMY_RX;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_rx = spi_data_len;
|
counter_rx = spi_data_len;
|
counter_rx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_rx = 1'b1;
|
spi_en_rx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
state_next = DATA_RX;
|
state_next = DATA_RX;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 532... |
Line 544... |
|
|
if(spi_dummy_wr_len != 0) begin
|
if(spi_dummy_wr_len != 0) begin
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
state_next = DUMMY;
|
spi_clock_en = tx_clk_en;
|
|
state_next = DUMMY_TX;
|
end else begin
|
end else begin
|
counter_tx = spi_data_len;
|
counter_tx = spi_data_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_valid = 1'b1;
|
ctrl_data_valid = 1'b1;
|
|
spi_clock_en = tx_clk_en;
|
state_next = DATA_TX;
|
state_next = DATA_TX;
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
else
|
| Line 549... |
Line 563... |
state_next = WAIT_EDGE;
|
state_next = WAIT_EDGE;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
DUMMY:
|
DUMMY_TX:
|
begin
|
begin
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
spi_status[4] = 1'b1;
|
spi_status[4] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = 1'b1;
|
spi_clock_en = 1'b1;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
|
|
if (tx_done) begin
|
if (tx_done && spi_fall) begin
|
if (spi_data_len != 0) begin
|
if (spi_data_len != 0) begin
|
if (do_rx) begin
|
if (do_rx) begin
|
counter_rx = spi_data_len;
|
counter_rx = spi_data_len;
|
counter_rx_valid = 1'b1;
|
counter_rx_valid = 1'b1;
|
spi_en_rx = 1'b1;
|
spi_en_rx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
state_next = DATA_RX;
|
state_next = DATA_RX;
|
end else begin
|
end else begin
|
counter_tx = spi_data_len;
|
counter_tx = spi_data_len;
|
counter_tx_valid = 1'b1;
|
counter_tx_valid = 1'b1;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
| Line 584... |
Line 599... |
end
|
end
|
else
|
else
|
begin
|
begin
|
ctrl_data_mux = DATA_EMPTY;
|
ctrl_data_mux = DATA_EMPTY;
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
state_next = DUMMY;
|
state_next = DUMMY_TX;
|
end
|
end
|
end
|
end
|
|
|
DATA_TX:
|
DUMMY_RX:
|
begin
|
begin
|
|
spi_en_rx = 1'b1;
|
spi_status[5] = 1'b1;
|
spi_status[5] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
|
spi_clock_en = 1'b1;
|
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
|
|
|
if (rx_done && spi_rise) begin
|
|
if (spi_data_len != 0) begin
|
|
if (do_rx) begin
|
|
counter_rx = spi_data_len;
|
|
counter_rx_valid = 1'b1;
|
|
spi_en_rx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
|
state_next = DATA_RX;
|
|
end else begin
|
|
counter_tx = spi_data_len;
|
|
counter_tx_valid = 1'b1;
|
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
|
|
|
spi_clock_en = tx_clk_en;
|
|
spi_en_tx = 1'b1;
|
|
state_next = DATA_TX;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
eot = 1'b1;
|
|
state_next = WAIT_EDGE;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
ctrl_data_mux = DATA_EMPTY;
|
|
spi_en_tx = 1'b1;
|
|
spi_clock_en = rx_clk_en;
|
|
state_next = DUMMY_RX;
|
|
end
|
|
end
|
|
DATA_TX:
|
|
begin
|
|
spi_status[6] = 1'b1;
|
|
spi_cs = 1'b0;
|
spi_clock_en = tx_clk_en;
|
spi_clock_en = tx_clk_en;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_mux = DATA_FIFO;
|
ctrl_data_valid = 1'b1;
|
|
spi_en_tx = 1'b1;
|
spi_en_tx = 1'b1;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
|
|
|
if (tx_done) begin
|
if (tx_done && spi_fall) begin
|
eot = 1'b1;
|
eot = 1'b1;
|
state_next = WAIT_EDGE;
|
state_next = WAIT_EDGE;
|
spi_clock_en = 1'b0;
|
spi_clock_en = 1'b0;
|
end else begin
|
end else begin
|
state_next = DATA_TX;
|
state_next = DATA_TX;
|
end
|
end
|
end
|
end
|
|
|
DATA_RX:
|
DATA_RX:
|
begin
|
begin
|
spi_status[6] = 1'b1;
|
spi_status[7] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = rx_clk_en;
|
spi_clock_en = rx_clk_en;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
|
|
if (rx_done) begin
|
if (rx_done && spi_rise) begin
|
state_next = WAIT_EDGE;
|
state_next = WAIT_EDGE;
|
end else begin
|
end else begin
|
spi_en_rx = 1'b1;
|
spi_en_rx = 1'b1;
|
state_next = DATA_RX;
|
state_next = DATA_RX;
|
end
|
end
|
end
|
end
|
WAIT_EDGE:
|
WAIT_EDGE:
|
begin
|
begin
|
spi_status[7] = 1'b1;
|
spi_status[8] = 1'b1;
|
spi_cs = 1'b0;
|
spi_cs = 1'b0;
|
spi_clock_en = 1'b0;
|
spi_clock_en = 1'b0;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
|
eot = 1'b1;
|
eot = 1'b1;
|
state_next = IDLE;
|
state_next = IDLE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
assign spi_ack = ((spi_req ==1) && (state_next == WAIT_EDGE)) ? 1'b1 : 1'b0;
|
assign spi_ack = ((spi_req ==1) && (state == WAIT_EDGE)) ? 1'b1 : 1'b0;
|
|
|
|
|
always_ff @(posedge clk, negedge rstn)
|
always_ff @(posedge clk, negedge rstn)
|
begin
|
begin
|
if (rstn == 1'b0)
|
if (rstn == 1'b0)
|
