| Line 64... |
Line 64... |
output logic wbd_ack_o, // acknowlegement
|
output logic wbd_ack_o, // acknowlegement
|
output logic wbd_err_o, // error
|
output logic wbd_err_o, // error
|
|
|
output logic [7:0] spi_clk_div,
|
output logic [7:0] spi_clk_div,
|
output logic spi_clk_div_valid,
|
output logic spi_clk_div_valid,
|
input logic [7:0] spi_status,
|
input logic [8:0] spi_status,
|
|
|
// Towards SPI TX/RX FSM
|
// Towards SPI TX/RX FSM
|
|
|
|
|
output logic spi_req,
|
output logic spi_req,
|
| Line 107... |
Line 107... |
parameter REG_STATUS = 4'b1000;
|
parameter REG_STATUS = 4'b1000;
|
|
|
// Init FSM
|
// Init FSM
|
parameter SPI_INIT_IDLE = 3'b000;
|
parameter SPI_INIT_IDLE = 3'b000;
|
parameter SPI_INIT_CMD_WAIT = 3'b001;
|
parameter SPI_INIT_CMD_WAIT = 3'b001;
|
parameter SPI_INIT_WRR_CMD = 3'b010;
|
parameter SPI_INIT_WREN_CMD = 3'b010;
|
parameter SPI_INIT_WRR_WAIT = 3'b011;
|
parameter SPI_INIT_WREN_WAIT = 3'b011;
|
|
parameter SPI_INIT_WRR_CMD = 3'b100;
|
|
parameter SPI_INIT_WRR_WAIT = 3'b101;
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Variable declartion
|
// Variable declartion
|
// -------------------------------------------------------
|
// -------------------------------------------------------
|
logic spi_init_done ;
|
logic spi_init_done ;
|
| Line 159... |
Line 161... |
assign spi_cmd = (spim_mem_req && !spim_wb_we) ? 8'hEB : reg2spi_cmd;
|
assign spi_cmd = (spim_mem_req && !spim_wb_we) ? 8'hEB : reg2spi_cmd;
|
assign spi_cmd_len = (spim_mem_req && !spim_wb_we) ? 8 : reg2spi_cmd_len;
|
assign spi_cmd_len = (spim_mem_req && !spim_wb_we) ? 8 : reg2spi_cmd_len;
|
assign spi_mode_cmd = (spim_mem_req && !spim_wb_we) ? 8'h00 : reg2spi_mode;
|
assign spi_mode_cmd = (spim_mem_req && !spim_wb_we) ? 8'h00 : reg2spi_mode;
|
assign spi_mode_cmd_enb = (spim_mem_req && !spim_wb_we) ? 1 : reg2spi_mode_enb;
|
assign spi_mode_cmd_enb = (spim_mem_req && !spim_wb_we) ? 1 : reg2spi_mode_enb;
|
assign spi_csreg = (spim_mem_req && !spim_wb_we) ? '1 : reg2spi_csreg;
|
assign spi_csreg = (spim_mem_req && !spim_wb_we) ? '1 : reg2spi_csreg;
|
assign spi_data_len = (spim_mem_req && !spim_wb_we) ? 'h10 : reg2spi_data_len;
|
assign spi_data_len = (spim_mem_req && !spim_wb_we) ? 'h20 : reg2spi_data_len;
|
assign spi_dummy_rd_len = (spim_mem_req && !spim_wb_we) ? 16 : reg2spi_dummy_rd_len;
|
assign spi_dummy_rd_len = (spim_mem_req && !spim_wb_we) ? 'h20 : reg2spi_dummy_rd_len;
|
assign spi_dummy_wr_len = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_dummy_wr_len;
|
assign spi_dummy_wr_len = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_dummy_wr_len;
|
assign spi_swrst = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_swrst;
|
assign spi_swrst = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_swrst;
|
assign spi_rd = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_rd;
|
assign spi_rd = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_rd;
|
assign spi_wr = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_wr;
|
assign spi_wr = (spim_mem_req && !spim_wb_we) ? 0 : reg2spi_wr;
|
assign spi_qrd = (spim_mem_req && !spim_wb_we) ? 1 : reg2spi_qrd;
|
assign spi_qrd = (spim_mem_req && !spim_wb_we) ? 1 : reg2spi_qrd;
|
| Line 198... |
Line 200... |
spim_wb_addr <= '0;
|
spim_wb_addr <= '0;
|
spim_wb_be <= '0;
|
spim_wb_be <= '0;
|
spim_wb_we <= '0;
|
spim_wb_we <= '0;
|
spim_wb_ack <= '0;
|
spim_wb_ack <= '0;
|
end else begin
|
end else begin
|
spim_wb_req <= wbd_stb_i;
|
if(spi_init_done) begin // Wait for internal SPI Init Done
|
|
spim_wb_req <= wbd_stb_i && (spi_ack == 0) && (spim_wb_ack==0);
|
spim_wb_req_l <= spim_wb_req;
|
spim_wb_req_l <= spim_wb_req;
|
spim_wb_wdata <= wbd_dat_i;
|
spim_wb_wdata <= wbd_dat_i;
|
spim_wb_addr <= wbd_adr_i;
|
spim_wb_addr <= wbd_adr_i;
|
spim_wb_be <= wbd_sel_i;
|
spim_wb_be <= wbd_sel_i;
|
spim_wb_we <= wbd_we_i;
|
spim_wb_we <= wbd_we_i;
|
| Line 212... |
Line 215... |
if(reg2spi_req && (reg2spi_rd || reg2spi_qrd ) && spi_ack)
|
if(reg2spi_req && (reg2spi_rd || reg2spi_qrd ) && spi_ack)
|
spim_reg_rdata <= spi_rdata;
|
spim_reg_rdata <= spi_rdata;
|
|
|
if(!spim_wb_we && spim_wb_req && spi_ack)
|
if(!spim_wb_we && spim_wb_req && spi_ack)
|
spim_wb_rdata <= spi_rdata;
|
spim_wb_rdata <= spi_rdata;
|
else
|
else if (spim_reg_req)
|
spim_wb_rdata <= reg_rdata;
|
spim_wb_rdata <= reg_rdata;
|
|
|
// For safer design, we have generated ack after 2 cycle latter to
|
// For safer design, we have generated ack after 2 cycle latter to
|
// cross-check current request is towards SPI or not
|
// cross-check current request is towards SPI or not
|
spim_wb_ack <= (spi_req) ? spi_ack :
|
spim_wb_ack <= (spi_req && spim_wb_req) ? spi_ack :
|
((spim_wb_ack==0) && spim_wb_req && spim_wb_req_l) ;
|
((spim_wb_ack==0) && spim_wb_req && spim_wb_req_l) ;
|
end
|
end
|
end
|
end
|
|
end
|
|
|
integer byte_index;
|
integer byte_index;
|
always_ff @(negedge rst_n or posedge mclk) begin
|
always_ff @(negedge rst_n or posedge mclk) begin
|
if ( rst_n == 1'b0 ) begin
|
if ( rst_n == 1'b0 ) begin
|
reg2spi_swrst <= 1'b0;
|
reg2spi_swrst <= 1'b0;
|
| Line 257... |
Line 261... |
reg2spi_wr <= 'h1; // SPI Write Req
|
reg2spi_wr <= 'h1; // SPI Write Req
|
reg2spi_qrd <= 'h0;
|
reg2spi_qrd <= 'h0;
|
reg2spi_qwr <= 'h0;
|
reg2spi_qwr <= 'h0;
|
reg2spi_swrst <= 'h0;
|
reg2spi_swrst <= 'h0;
|
reg2spi_csreg <= 'h1;
|
reg2spi_csreg <= 'h1;
|
reg2spi_cmd[7:0] <= 'h6; // WREN command
|
reg2spi_cmd[7:0] <= 'hAB; // POWER UP command
|
reg2spi_mode[7:0] <= 'h0;
|
reg2spi_mode[7:0] <= 'h0;
|
reg2spi_cmd_len <= 'h8;
|
reg2spi_cmd_len <= 'h8;
|
reg2spi_addr_len <= 'h0;
|
reg2spi_addr_len <= 'h0;
|
reg2spi_data_len <= 'h0;
|
reg2spi_data_len <= 'h0;
|
reg2spi_wdata <= 'h0;
|
reg2spi_wdata <= 'h0;
|
| Line 270... |
Line 274... |
end
|
end
|
SPI_INIT_CMD_WAIT:
|
SPI_INIT_CMD_WAIT:
|
begin
|
begin
|
if(spi_ack) begin
|
if(spi_ack) begin
|
reg2spi_req <= 1'b0;
|
reg2spi_req <= 1'b0;
|
|
spi_init_state <= SPI_INIT_WREN_CMD;
|
|
end
|
|
end
|
|
SPI_INIT_WREN_CMD:
|
|
begin
|
|
reg2spi_rd <= 'h0;
|
|
reg2spi_wr <= 'h1; // SPI Write Req
|
|
reg2spi_qrd <= 'h0;
|
|
reg2spi_qwr <= 'h0;
|
|
reg2spi_swrst <= 'h0;
|
|
reg2spi_csreg <= 'h1;
|
|
reg2spi_cmd[7:0] <= 'h6; // WREN command
|
|
reg2spi_mode[7:0] <= 'h0;
|
|
reg2spi_cmd_len <= 'h8;
|
|
reg2spi_addr_len <= 'h0;
|
|
reg2spi_data_len <= 'h0;
|
|
reg2spi_wdata <= 'h0;
|
|
reg2spi_req <= 'h1;
|
|
spi_init_state <= SPI_INIT_WREN_WAIT;
|
|
end
|
|
SPI_INIT_WREN_WAIT:
|
|
begin
|
|
if(spi_ack) begin
|
|
reg2spi_req <= 1'b0;
|
spi_init_state <= SPI_INIT_WRR_CMD;
|
spi_init_state <= SPI_INIT_WRR_CMD;
|
end
|
end
|
end
|
end
|
SPI_INIT_WRR_CMD:
|
SPI_INIT_WRR_CMD:
|
begin
|
begin
|
| Line 370... |
Line 398... |
reg2spi_req <= 1'b0;
|
reg2spi_req <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
wire [3:0] reg_addr = spim_wb_addr[7:4];
|
|
|
// implement slave model register read mux
|
// implement slave model register read mux
|
always_comb
|
always_comb
|
begin
|
begin
|
reg_rdata = '0;
|
reg_rdata = '0;
|
case(spim_wb_addr[7:4])
|
if(spim_reg_req) begin
|
|
case(reg_addr)
|
REG_CTRL:
|
REG_CTRL:
|
reg_rdata[31:0] = { 20'h0,
|
reg_rdata[31:0] = { 20'h0,
|
reg2spi_csreg,
|
reg2spi_csreg,
|
3'b0,
|
3'b0,
|
reg2spi_swrst,
|
reg2spi_swrst,
|
| Line 400... |
Line 432... |
REG_SPIWDATA:
|
REG_SPIWDATA:
|
reg_rdata[31:0] = reg2spi_wdata;
|
reg_rdata[31:0] = reg2spi_wdata;
|
REG_SPIRDATA:
|
REG_SPIRDATA:
|
reg_rdata[31:0] = spim_reg_rdata;
|
reg_rdata[31:0] = spim_reg_rdata;
|
REG_STATUS:
|
REG_STATUS:
|
reg_rdata[31:0] = {24'h0,spi_status};
|
reg_rdata[31:0] = {23'h0,spi_status};
|
endcase
|
endcase
|
end
|
end
|
|
end
|
|
|
|
|
endmodule
|
endmodule
|
