//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// SPI RX Module ////
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//// SPI RX Module ////
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//// ////
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//// ////
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//// This file is part of the YIFive cores project ////
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//// This file is part of the YIFive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// SPI RX module ////
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//// SPI RX module ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//// Revision : ////
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//// V.0 - June 8, 2021 ////
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//// V.0 - June 8, 2021 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module spim_rx #(
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module spim_rx #(
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parameter ENDIEAN = 0 // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0
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parameter ENDIEAN = 0 // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0
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)
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)
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(
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(
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input logic clk,
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input logic clk,
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input logic rstn,
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input logic rstn,
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input logic en,
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input logic en,
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input logic rx_edge,
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input logic rx_edge,
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output logic rx_done,
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output logic rx_done,
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input logic sdi0,
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input logic sdi0,
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input logic sdi1,
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input logic sdi1,
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input logic sdi2,
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input logic sdi2,
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input logic sdi3,
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input logic sdi3,
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input logic en_quad_in,
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input logic en_quad_in,
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input logic [15:0] counter_in,
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input logic [15:0] counter_in,
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input logic counter_in_upd,
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input logic counter_in_upd,
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output logic [31:0] data,
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output logic [31:0] data,
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input logic data_ready,
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input logic data_ready,
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output logic data_valid,
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output logic data_valid,
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output logic clk_en_o
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output logic clk_en_o
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);
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);
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logic [31:0] data_int;
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logic [31:0] data_int;
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logic [31:0] data_int_next;
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logic [31:0] data_int_next;
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logic [15:0] counter;
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logic [15:0] counter;
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logic [15:0] counter_trgt;
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logic [15:0] counter_trgt;
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logic [15:0] counter_next;
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logic [15:0] counter_next;
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logic [15:0] counter_trgt_next;
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logic reg_done;
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logic reg_done;
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enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
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enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
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assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
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assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
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// RISV is little endian, so data is converted to little endian format
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// RISV is little endian, so data is converted to little endian format
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assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
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assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
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assign rx_done = (counter == (counter_trgt-1)) & rx_edge;
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always_comb
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begin
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if (counter_in_upd)
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counter_trgt_next = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
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else
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counter_trgt_next = counter_trgt;
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end
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always_comb
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always_comb
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begin
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begin
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rx_NS = rx_CS;
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rx_NS = rx_CS;
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clk_en_o = 1'b0;
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data_int_next = data_int;
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data_int_next = data_int;
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data_valid = 1'b0;
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data_valid = 1'b0;
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counter_next = counter;
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counter_next = counter;
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case (rx_CS)
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case (rx_CS)
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IDLE: begin
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IDLE: begin
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clk_en_o = 1'b0;
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// check first if there is available space instead of later
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// check first if there is available space instead of later
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if (en) begin
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if (en) begin
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rx_NS = RECEIVE;
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rx_NS = RECEIVE;
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end
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end
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end
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end
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RECEIVE: begin
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RECEIVE: begin
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clk_en_o = 1'b1;
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if (rx_edge) begin
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if (rx_edge) begin
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counter_next = counter + 1;
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counter_next = counter + 1;
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if (en_quad_in)
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if (en_quad_in)
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data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};
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data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};
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else
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else
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data_int_next = {data_int[30:0],sdi1};
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data_int_next = {data_int[30:0],sdi1};
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if (rx_done) begin
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if (rx_done) begin
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counter_next = 0;
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counter_next = 0;
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data_valid = 1'b1;
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data_valid = 1'b1;
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if (data_ready)
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if (data_ready)
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rx_NS = IDLE;
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rx_NS = IDLE;
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else
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else
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rx_NS = WAIT_FIFO_DONE;
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rx_NS = WAIT_FIFO_DONE;
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end else if (reg_done) begin
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end else if (reg_done) begin
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data_valid = 1'b1;
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data_valid = 1'b1;
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if (~data_ready) begin
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if (~data_ready) begin
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// no space in the FIFO, wait for free space
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// no space in the FIFO, wait for free space
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clk_en_o = 1'b0;
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rx_NS = WAIT_FIFO;
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rx_NS = WAIT_FIFO;
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end
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end
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end
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end
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end
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end
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end
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end
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WAIT_FIFO_DONE: begin
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WAIT_FIFO_DONE: begin
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data_valid = 1'b1;
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data_valid = 1'b1;
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if (data_ready)
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if (data_ready)
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rx_NS = IDLE;
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rx_NS = IDLE;
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end
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end
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WAIT_FIFO: begin
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WAIT_FIFO: begin
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data_valid = 1'b1;
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data_valid = 1'b1;
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if (data_ready)
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if (data_ready)
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rx_NS = RECEIVE;
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rx_NS = RECEIVE;
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end
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end
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endcase
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endcase
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end
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end
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always_ff @(posedge clk, negedge rstn)
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always_ff @(posedge clk, negedge rstn)
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begin
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begin
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if (rstn == 0)
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if (rstn == 0)
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begin
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begin
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counter <= 0;
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counter <= 0;
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counter_trgt <= 'h8;
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counter_trgt <= 'h8;
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data_int <= '0;
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data_int <= '0;
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rx_done <= '0;
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clk_en_o <= '0;
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rx_CS <= IDLE;
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rx_CS <= IDLE;
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end
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end
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else
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else
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begin
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begin
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if (rx_edge) begin
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counter <= counter_next;
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counter <= counter_next;
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counter_trgt <= counter_trgt_next;
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data_int <= data_int_next;
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data_int <= data_int_next;
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rx_CS <= rx_NS;
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rx_CS <= rx_NS;
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rx_done <= (counter_next == (counter_trgt-1)) && (rx_NS == RECEIVE);
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clk_en_o <= (rx_NS == RECEIVE);
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end
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if (en && counter_in_upd) begin
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counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
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end
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end
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end
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end
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end
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endmodule
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endmodule
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