URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_top.sv] - Diff between revs 18 and 20

Rev 18	Rev 20
Line 51...	Line 51...
`(`	`(`
`input logic mclk,`	`input logic mclk,`
`input logic rst_n,`	`input logic rst_n,`


`output logic wbd_stb_i, // strobe/request`	`input logic wbd_stb_i, // strobe/request`
`output logic [WB_WIDTH-1:0] wbd_adr_i, // address`	`input logic [WB_WIDTH-1:0] wbd_adr_i, // address`
`output logic wbd_we_i, // write`	`input logic wbd_we_i, // write`
`output logic [WB_WIDTH-1:0] wbd_dat_i, // data output`	`input logic [WB_WIDTH-1:0] wbd_dat_i, // data output`
`output logic [3:0] wbd_sel_i, // byte enable`	`input logic [3:0] wbd_sel_i, // byte enable`
`input logic [WB_WIDTH-1:0] wbd_dat_o, // data input`	`output logic [WB_WIDTH-1:0] wbd_dat_o, // data input`
`input logic wbd_ack_o, // acknowlegement`	`output logic wbd_ack_o, // acknowlegement`
`input logic wbd_err_o, // error`	`output logic wbd_err_o, // error`

`output logic [1:0] events_o,`	`output logic [1:0] events_o,`

`output logic spi_clk,`	`output logic spi_clk,`
`output logic spi_csn0,`	`output logic spi_csn0,`