OpenCores
URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_top.sv] - Diff between revs 20 and 21

Show entire file | Details | Blame | View Log

Rev 20 Rev 21
Line 83... Line 83...
 
 
 
 
 
 
    logic   [7:0] spi_clk_div;
    logic   [7:0] spi_clk_div;
    logic         spi_clk_div_valid;
    logic         spi_clk_div_valid;
    logic   [7:0] spi_status;
    logic         spi_req;
 
    logic         spi_ack;
    logic  [31:0] spi_addr;
    logic  [31:0] spi_addr;
    logic   [5:0] spi_addr_len;
    logic   [5:0] spi_addr_len;
    logic  [7:0]  spi_cmd;
    logic  [7:0]  spi_cmd;
    logic   [5:0] spi_cmd_len;
    logic   [5:0] spi_cmd_len;
    logic  [7:0]  spi_mode_cmd;
    logic  [7:0]  spi_mode_cmd;
Line 107... Line 108...
    logic         spi_data_tx_valid;
    logic         spi_data_tx_valid;
    logic         spi_data_tx_ready;
    logic         spi_data_tx_ready;
    logic  [31:0] spi_data_rx;
    logic  [31:0] spi_data_rx;
    logic         spi_data_rx_valid;
    logic         spi_data_rx_valid;
    logic         spi_data_rx_ready;
    logic         spi_data_rx_ready;
    logic   [7:0] spi_ctrl_status;
    logic   [8:0] spi_ctrl_status;
    logic  [31:0] spi_ctrl_data_tx;
    logic  [31:0] spi_ctrl_data_tx;
    logic         spi_ctrl_data_tx_valid;
    logic         spi_ctrl_data_tx_valid;
    logic         spi_ctrl_data_tx_ready;
    logic         spi_ctrl_data_tx_ready;
    logic  [31:0] spi_ctrl_data_rx;
    logic  [31:0] spi_ctrl_data_rx;
    logic         spi_ctrl_data_rx_valid;
    logic         spi_ctrl_data_rx_valid;
Line 142... Line 143...
        .wbd_ack_o                      (wbd_ack_o                    ), // acknowlegement
        .wbd_ack_o                      (wbd_ack_o                    ), // acknowlegement
        .wbd_err_o                      (wbd_err_o                    ),  // error
        .wbd_err_o                      (wbd_err_o                    ),  // error
 
 
        .spi_clk_div                    (spi_clk_div                  ),
        .spi_clk_div                    (spi_clk_div                  ),
        .spi_clk_div_valid              (spi_clk_div_valid            ),
        .spi_clk_div_valid              (spi_clk_div_valid            ),
        .spi_status                     (spi_status                   ),
        .spi_status                     (spi_ctrl_status              ),
 
 
 
 
        .spi_req                        (spi_req                     ),
        .spi_req                        (spi_req                     ),
        .spi_addr                       (spi_addr                     ),
        .spi_addr                       (spi_addr                     ),
        .spi_addr_len                   (spi_addr_len                 ),
        .spi_addr_len                   (spi_addr_len                 ),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.