| Line 102... |
Line 102... |
input logic csr2exu_mstatus_mie_up_i, // MSTATUS or MIE update in the current cycle
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input logic csr2exu_mstatus_mie_up_i, // MSTATUS or MIE update in the current cycle
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// EXU <-> DMEM interface
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// EXU <-> DMEM interface
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output logic exu2dmem_req_o, // Data memory request
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output logic exu2dmem_req_o, // Data memory request
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output logic exu2dmem_cmd_o, // Data memory command - cp.7
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output logic exu2dmem_cmd_o, // Data memory command - cp.7
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output type_scr1_mem_width_e exu2dmem_width_o, // Data memory width
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output logic [1:0] exu2dmem_width_o, // Data memory width
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output logic [`SCR1_DMEM_AWIDTH-1:0] exu2dmem_addr_o, // Data memory address
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output logic [`SCR1_DMEM_AWIDTH-1:0] exu2dmem_addr_o, // Data memory address
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output logic [`SCR1_DMEM_DWIDTH-1:0] exu2dmem_wdata_o, // Data memory write data
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output logic [`SCR1_DMEM_DWIDTH-1:0] exu2dmem_wdata_o, // Data memory write data
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input logic dmem2exu_req_ack_i, // Data memory request acknowledge
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input logic dmem2exu_req_ack_i, // Data memory request acknowledge
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2exu_rdata_i, // Data memory read data
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2exu_rdata_i, // Data memory read data
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input logic [1:0] dmem2exu_resp_i, // Data memory response - cp.7
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input logic [1:0] dmem2exu_resp_i, // Data memory response - cp.7
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| Line 165... |
Line 165... |
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Local types declaration
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// Local types declaration
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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typedef enum logic {
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//typedef enum logic {
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SCR1_CSR_INIT,
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parameter SCR1_CSR_INIT = 1'b0;
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SCR1_CSR_RDY
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parameter SCR1_CSR_RDY = 1'b1;
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} scr1_csr_access_e;
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//} scr1_csr_access_e;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Local signals declaration
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// Local signals declaration
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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| Line 278... |
Line 278... |
logic [`SCR1_MPRF_AWIDTH-1:0] mprf_rs2_addr;
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logic [`SCR1_MPRF_AWIDTH-1:0] mprf_rs2_addr;
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// CSR signals
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// CSR signals
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// CSR access register
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// CSR access register
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scr1_csr_access_e csr_access_ff;
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logic csr_access_ff;
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scr1_csr_access_e csr_access_next;
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logic csr_access_next;
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logic csr_access_init;
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logic csr_access_init;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Instruction execution queue
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// Instruction execution queue
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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