| Line 38... |
Line 38... |
input logic pipe2ifu_stop_fetch_i, // Stop instruction fetch
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input logic pipe2ifu_stop_fetch_i, // Stop instruction fetch
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// IFU <-> IMEM interface
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// IFU <-> IMEM interface
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input logic imem2ifu_req_ack_i, // Instruction memory request acknowledgement
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input logic imem2ifu_req_ack_i, // Instruction memory request acknowledgement
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output logic ifu2imem_req_o, // Instruction memory request
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output logic ifu2imem_req_o, // Instruction memory request
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output type_scr1_mem_cmd_e ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
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output logic ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
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output logic [`SCR1_IMEM_AWIDTH-1:0] ifu2imem_addr_o, // Instruction memory address
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output logic [`SCR1_IMEM_AWIDTH-1:0] ifu2imem_addr_o, // Instruction memory address
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input logic [`SCR1_IMEM_DWIDTH-1:0] imem2ifu_rdata_i, // Instruction memory read data
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input logic [`SCR1_IMEM_DWIDTH-1:0] imem2ifu_rdata_i, // Instruction memory read data
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input type_scr1_mem_resp_e imem2ifu_resp_i, // Instruction memory response
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input logic [1:0] imem2ifu_resp_i, // Instruction memory response
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// IFU <-> EXU New PC interface
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// IFU <-> EXU New PC interface
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input logic exu2ifu_pc_new_req_i, // New PC request (jumps, branches, traps etc)
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input logic exu2ifu_pc_new_req_i, // New PC request (jumps, branches, traps etc)
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input logic [`SCR1_XLEN-1:0] exu2ifu_pc_new_i, // New PC
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input logic [`SCR1_XLEN-1:0] exu2ifu_pc_new_i, // New PC
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| Line 86... |
Line 86... |
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Local types declaration
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// Local types declaration
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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typedef enum logic {
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//typedef enum logic {
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SCR1_IFU_FSM_IDLE,
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parameter SCR1_IFU_FSM_IDLE = 1'b0;
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SCR1_IFU_FSM_FETCH
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parameter SCR1_IFU_FSM_FETCH = 1'b1;
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} type_scr1_ifu_fsm_e;
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//} type_scr1_ifu_fsm_e;
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typedef enum logic[1:0] {
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//typedef enum logic[1:0] {
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SCR1_IFU_QUEUE_WR_NONE, // No write to queue
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parameter SCR1_IFU_QUEUE_WR_NONE = 2'b00; // No write to queue
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SCR1_IFU_QUEUE_WR_FULL, // Write 32 rdata bits to queue
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parameter SCR1_IFU_QUEUE_WR_FULL = 2'b01; // Write 32 rdata bits to queue
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SCR1_IFU_QUEUE_WR_HI // Write 16 upper rdata bits to queue
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parameter SCR1_IFU_QUEUE_WR_HI = 2'b10; // Write 16 upper rdata bits to queue
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} type_scr1_ifu_queue_wr_e;
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//} type_scr1_ifu_queue_wr_e;
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typedef enum logic[1:0] {
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//typedef enum logic[1:0] {
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SCR1_IFU_QUEUE_RD_NONE, // No queue read
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parameter SCR1_IFU_QUEUE_RD_NONE = 2'b00; // No queue read
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SCR1_IFU_QUEUE_RD_HWORD, // Read halfword
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parameter SCR1_IFU_QUEUE_RD_HWORD = 2'b01; // Read halfword
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SCR1_IFU_QUEUE_RD_WORD // Read word
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parameter SCR1_IFU_QUEUE_RD_WORD = 2'b10; // Read word
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} type_scr1_ifu_queue_rd_e;
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//} type_scr1_ifu_queue_rd_e;
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`ifdef SCR1_NO_DEC_STAGE
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`ifdef SCR1_NO_DEC_STAGE
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typedef enum logic[1:0] {
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typedef enum logic[1:0] {
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SCR1_BYPASS_NONE, // No bypass
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SCR1_BYPASS_NONE, // No bypass
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SCR1_BYPASS_RVC, // Bypass RVC
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SCR1_BYPASS_RVC, // Bypass RVC
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SCR1_BYPASS_RVI_RDATA_QUEUE, // Bypass RVI, rdata+queue
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SCR1_BYPASS_RVI_RDATA_QUEUE, // Bypass RVI, rdata+queue
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SCR1_BYPASS_RVI_RDATA // Bypass RVI, rdata only
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SCR1_BYPASS_RVI_RDATA // Bypass RVI, rdata only
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} type_scr1_bypass_e;
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} type_scr1_bypass_e;
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`endif // SCR1_NO_DEC_STAGE
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`endif // SCR1_NO_DEC_STAGE
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typedef enum logic [2:0] {
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//typedef enum logic [2:0] {
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// SCR1_IFU_INSTR__
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// SCR1_IFU_INSTR__
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SCR1_IFU_INSTR_NONE, // No valid instruction
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parameter SCR1_IFU_INSTR_NONE = 3'b000 ; // No valid instruction
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SCR1_IFU_INSTR_RVI_HI_RVI_LO, // Full RV32I instruction
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parameter SCR1_IFU_INSTR_RVI_HI_RVI_LO = 3'b001 ; // Full RV32I instruction
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SCR1_IFU_INSTR_RVC_RVC,
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parameter SCR1_IFU_INSTR_RVC_RVC = 3'b010 ;
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SCR1_IFU_INSTR_RVI_LO_RVC,
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parameter SCR1_IFU_INSTR_RVI_LO_RVC = 3'b011 ;
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SCR1_IFU_INSTR_RVC_RVI_HI,
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parameter SCR1_IFU_INSTR_RVC_RVI_HI = 3'b100 ;
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SCR1_IFU_INSTR_RVI_LO_RVI_HI,
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parameter SCR1_IFU_INSTR_RVI_LO_RVI_HI = 3'b101 ;
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SCR1_IFU_INSTR_RVC_NV, // Instruction after unaligned new_pc
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parameter SCR1_IFU_INSTR_RVC_NV = 3'b110 ; // Instruction after unaligned new_pc
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SCR1_IFU_INSTR_RVI_LO_NV // Instruction after unaligned new_pc
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parameter SCR1_IFU_INSTR_RVI_LO_NV = 3'b111 ; // Instruction after unaligned new_pc
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} type_scr1_ifu_instr_e;
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//} type_scr1_ifu_instr_e;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Local signals declaration
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// Local signals declaration
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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| Line 139... |
Line 139... |
logic new_pc_unaligned_upd;
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logic new_pc_unaligned_upd;
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// IMEM instruction type decoder
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// IMEM instruction type decoder
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logic instr_hi_is_rvi;
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logic instr_hi_is_rvi;
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logic instr_lo_is_rvi;
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logic instr_lo_is_rvi;
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type_scr1_ifu_instr_e instr_type;
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logic [2:0] instr_type;
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// Register to store if the previous IMEM instruction had low part of RVI instruction
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// Register to store if the previous IMEM instruction had low part of RVI instruction
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// in its high part
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// in its high part
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logic instr_hi_rvi_lo_ff;
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logic instr_hi_rvi_lo_ff;
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logic instr_hi_rvi_lo_next;
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logic instr_hi_rvi_lo_next;
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// Queue read/write size decoders
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// Queue read/write size decoders
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type_scr1_ifu_queue_rd_e q_rd_size;
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logic [1:0] q_rd_size;
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logic q_rd_vd;
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logic q_rd_vd;
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logic q_rd_none;
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logic q_rd_none;
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logic q_rd_hword;
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logic q_rd_hword;
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type_scr1_ifu_queue_wr_e q_wr_size;
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logic [1:0] q_wr_size;
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logic q_wr_none;
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logic q_wr_none;
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logic q_wr_full;
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logic q_wr_full;
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// Write/read pointer registers
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// Write/read pointer registers
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logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_rptr;
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logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_rptr;
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| Line 194... |
Line 194... |
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// IFU FSM control signals
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// IFU FSM control signals
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logic ifu_fetch_req;
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logic ifu_fetch_req;
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logic ifu_stop_req;
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logic ifu_stop_req;
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type_scr1_ifu_fsm_e ifu_fsm_curr;
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logic ifu_fsm_curr;
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type_scr1_ifu_fsm_e ifu_fsm_next;
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logic ifu_fsm_next;
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logic ifu_fsm_fetch;
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logic ifu_fsm_fetch;
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// IMEM signals
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// IMEM signals
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//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
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|
