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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [pipeline/] [scr1_pipe_lsu.sv] - Diff between revs 11 and 21

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Rev 11 Rev 21
Line 49... Line 49...
    input   logic                               tdu2lsu_dbrkpt_exc_req_i,   // Data BP exception request
    input   logic                               tdu2lsu_dbrkpt_exc_req_i,   // Data BP exception request
`endif // SCR1_TDU_EN
`endif // SCR1_TDU_EN
 
 
    // LSU <-> DMEM interface
    // LSU <-> DMEM interface
    output  logic                               lsu2dmem_req_o,             // Data memory request
    output  logic                               lsu2dmem_req_o,             // Data memory request
    output  type_scr1_mem_cmd_e                 lsu2dmem_cmd_o,             // Data memory command (READ/WRITE)
    output  logic                               lsu2dmem_cmd_o,             // Data memory command (READ/WRITE)
    output  type_scr1_mem_width_e               lsu2dmem_width_o,           // Data memory data width
    output  logic [1:0]                         lsu2dmem_width_o,           // Data memory data width
    output  logic [`SCR1_DMEM_AWIDTH-1:0]       lsu2dmem_addr_o,            // Data memory address
    output  logic [`SCR1_DMEM_AWIDTH-1:0]       lsu2dmem_addr_o,            // Data memory address
    output  logic [`SCR1_DMEM_DWIDTH-1:0]       lsu2dmem_wdata_o,           // Data memory write data
    output  logic [`SCR1_DMEM_DWIDTH-1:0]       lsu2dmem_wdata_o,           // Data memory write data
    input   logic                               dmem2lsu_req_ack_i,         // Data memory request acknowledge
    input   logic                               dmem2lsu_req_ack_i,         // Data memory request acknowledge
    input   logic [`SCR1_DMEM_DWIDTH-1:0]       dmem2lsu_rdata_i,           // Data memory read data
    input   logic [`SCR1_DMEM_DWIDTH-1:0]       dmem2lsu_rdata_i,           // Data memory read data
    input   type_scr1_mem_resp_e                dmem2lsu_resp_i             // Data memory response
    input   logic [1:0]                         dmem2lsu_resp_i             // Data memory response
);
);
 
 
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Local types declaration
// Local types declaration
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
 
 
typedef enum logic {
//typedef enum logic {
    SCR1_LSU_FSM_IDLE,
parameter  SCR1_LSU_FSM_IDLE = 1'b0;
    SCR1_LSU_FSM_BUSY
parameter  SCR1_LSU_FSM_BUSY = 1'b1;
} type_scr1_lsu_fsm_e;
//} type_scr1_lsu_fsm_e;
 
 
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Local signals declaration
// Local signals declaration
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
 
 
// LSU FSM signals
// LSU FSM signals
type_scr1_lsu_fsm_e         lsu_fsm_curr;       // LSU FSM current state
logic                       lsu_fsm_curr;       // LSU FSM current state
type_scr1_lsu_fsm_e         lsu_fsm_next;       // LSU FSM next state
logic                       lsu_fsm_next;       // LSU FSM next state
logic                       lsu_fsm_idle;       // LSU FSM is in IDLE state
logic                       lsu_fsm_idle;       // LSU FSM is in IDLE state
 
 
// LSU Command register signals
// LSU Command register signals
logic                       lsu_cmd_upd;        // LSU Command register update
logic                       lsu_cmd_upd;        // LSU Command register update
type_scr1_lsu_cmd_sel_e     lsu_cmd_ff;         // LSU Command register value
type_scr1_lsu_cmd_sel_e     lsu_cmd_ff;         // LSU Command register value

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