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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @file
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/// @brief SCR1 pipeline top
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/// @brief SCR1 pipeline top
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///
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///
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//----------------------------------------------------------------------------------
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// project : YiFive
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// Rev: June 10, 2021, Dinesh A
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// Bugfix- reset correction for scr1_pipe_tdu when debug is not enabled
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// Note: previously reset rst_n is floating at simulation is failing
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// when SCR1_DBG_EN is disabled
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//---------------------------------------------------------------------------------
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`include "scr1_arch_description.svh"
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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`include "scr1_memif.svh"
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`include "scr1_riscv_isa_decoding.svh"
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`include "scr1_riscv_isa_decoding.svh"
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`include "scr1_csr.svh"
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`include "scr1_csr.svh"
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`endif // SCR1_DBG_EN
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`endif // SCR1_DBG_EN
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input logic clk, // Pipe clock
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input logic clk, // Pipe clock
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// Instruction Memory Interface
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// Instruction Memory Interface
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output logic pipe2imem_req_o, // IMEM request
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output logic pipe2imem_req_o, // IMEM request
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output type_scr1_mem_cmd_e pipe2imem_cmd_o, // IMEM command
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output logic pipe2imem_cmd_o, // IMEM command
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output logic [`SCR1_IMEM_AWIDTH-1:0] pipe2imem_addr_o, // IMEM address
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output logic [`SCR1_IMEM_AWIDTH-1:0] pipe2imem_addr_o, // IMEM address
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input logic imem2pipe_req_ack_i, // IMEM request acknowledge
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input logic imem2pipe_req_ack_i, // IMEM request acknowledge
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input logic [`SCR1_IMEM_DWIDTH-1:0] imem2pipe_rdata_i, // IMEM read data
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input logic [`SCR1_IMEM_DWIDTH-1:0] imem2pipe_rdata_i, // IMEM read data
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input type_scr1_mem_resp_e imem2pipe_resp_i, // IMEM response
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input logic [1:0] imem2pipe_resp_i, // IMEM response
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// Data Memory Interface
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// Data Memory Interface
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output logic pipe2dmem_req_o, // DMEM request
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output logic pipe2dmem_req_o, // DMEM request
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output type_scr1_mem_cmd_e pipe2dmem_cmd_o, // DMEM command
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output logic pipe2dmem_cmd_o, // DMEM command
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output type_scr1_mem_width_e pipe2dmem_width_o, // DMEM data width
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output logic [1:0] pipe2dmem_width_o, // DMEM data width
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output logic [`SCR1_DMEM_AWIDTH-1:0] pipe2dmem_addr_o, // DMEM address
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output logic [`SCR1_DMEM_AWIDTH-1:0] pipe2dmem_addr_o, // DMEM address
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output logic [`SCR1_DMEM_DWIDTH-1:0] pipe2dmem_wdata_o, // DMEM write data
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output logic [`SCR1_DMEM_DWIDTH-1:0] pipe2dmem_wdata_o, // DMEM write data
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input logic dmem2pipe_req_ack_i, // DMEM request acknowledge
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input logic dmem2pipe_req_ack_i, // DMEM request acknowledge
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2pipe_rdata_i, // DMEM read data
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2pipe_rdata_i, // DMEM read data
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input type_scr1_mem_resp_e dmem2pipe_resp_i, // DMEM response
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input logic [1:0] dmem2pipe_resp_i, // DMEM response
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`ifdef SCR1_DBG_EN
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`ifdef SCR1_DBG_EN
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// Debug interface:
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// Debug interface:
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input logic dbg_en, // 1 - debug operations enabled
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input logic dbg_en, // 1 - debug operations enabled
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// DM <-> Pipeline: HART Run Control i/f
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// DM <-> Pipeline: HART Run Control i/f
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// EXU <-> CSR event interface
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// EXU <-> CSR event interface
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logic exu2csr_take_irq; // Take IRQ trap
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logic exu2csr_take_irq; // Take IRQ trap
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logic exu2csr_take_exc; // Take exception trap
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logic exu2csr_take_exc; // Take exception trap
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logic exu2csr_mret_update; // MRET update CSR
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logic exu2csr_mret_update; // MRET update CSR
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logic exu2csr_mret_instr; // MRET instruction
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logic exu2csr_mret_instr; // MRET instruction
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type_scr1_exc_code_e exu2csr_exc_code; // Exception code (see scr1_arch_types.svh)
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logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code; // Exception code (see scr1_arch_types.svh)
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logic [`SCR1_XLEN-1:0] exu2csr_trap_val; // Trap value
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logic [`SCR1_XLEN-1:0] exu2csr_trap_val; // Trap value
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logic [`SCR1_XLEN-1:0] csr2exu_new_pc; // Exception/IRQ/MRET new PC
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logic [`SCR1_XLEN-1:0] csr2exu_new_pc; // Exception/IRQ/MRET new PC
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logic csr2exu_irq; // IRQ request
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logic csr2exu_irq; // IRQ request
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logic csr2exu_ip_ie; // Some IRQ pending and locally enabled
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logic csr2exu_ip_ie; // Some IRQ pending and locally enabled
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logic csr2exu_mstatus_mie_up; // MSTATUS or MIE update in the current cycle
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logic csr2exu_mstatus_mie_up; // MSTATUS or MIE update in the current cycle
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scr1_pipe_tdu i_pipe_tdu (
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scr1_pipe_tdu i_pipe_tdu (
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// Common signals
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// Common signals
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`ifdef SCR1_DBG_EN
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`ifdef SCR1_DBG_EN
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.rst_n (dbg_rst_n ),
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.rst_n (dbg_rst_n ),
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`else
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`else
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.rst_n (rst_n ),
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.rst_n (pipe_rst_n ), // dinesh-a: Bugfix- reset correction when debug is not enabled
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`endif // SCR1_DBG_EN
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`endif // SCR1_DBG_EN
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.clk (clk ),
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.clk (clk ),
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.clk_en (1'b1 ),
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.clk_en (1'b1 ),
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`ifdef SCR1_DBG_EN
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`ifdef SCR1_DBG_EN
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.tdu_dsbl_i (hwbrk_dsbl ),
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.tdu_dsbl_i (hwbrk_dsbl ),
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