URL https://opencores.org/ocsvn/yifive/yifive/trunk

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [includes/] [scr1_arch_types.svh] - Diff between revs 11 and 21

Rev 11	Rev 21
Line 18...	Line 18...
`else // SCR1_RVE_EXT	`else // SCR1_RVE_EXT
`define SCR1_MPRF_AWIDTH 5	`define SCR1_MPRF_AWIDTH 5
`define SCR1_MPRF_SIZE 32	`define SCR1_MPRF_SIZE 32
`endif // SCR1_RVE_EXT	`endif // SCR1_RVE_EXT

typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v;	`// Masked due to iverilog issue`
typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v;	//typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v;
	//typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v;

`parameter int unsigned SCR1_CSR_ADDR_WIDTH = 12;`	`parameter int unsigned SCR1_CSR_ADDR_WIDTH = 12;`
`parameter int unsigned SCR1_CSR_MTVEC_BASE_ZERO_BITS = 6;`	`parameter int unsigned SCR1_CSR_MTVEC_BASE_ZERO_BITS = 6;`
parameter int unsigned SCR1_CSR_MTVEC_BASE_VAL_BITS = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;	parameter int unsigned SCR1_CSR_MTVEC_BASE_VAL_BITS = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;
parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_WR_RST_VAL =	parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_WR_RST_VAL =