/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @file
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/// @brief Pipeline types description file
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/// @brief Pipeline types description file
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///
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///
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`ifndef SCR1_ARCH_TYPES_SVH
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`ifndef SCR1_ARCH_TYPES_SVH
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`define SCR1_ARCH_TYPES_SVH
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`define SCR1_ARCH_TYPES_SVH
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`include "scr1_arch_description.svh"
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`include "scr1_arch_description.svh"
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// MPRF and CSR parameters
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// MPRF and CSR parameters
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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`ifdef SCR1_RVE_EXT
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`ifdef SCR1_RVE_EXT
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`define SCR1_MPRF_AWIDTH 4
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`define SCR1_MPRF_AWIDTH 4
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`define SCR1_MPRF_SIZE 16
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`define SCR1_MPRF_SIZE 16
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`else // SCR1_RVE_EXT
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`else // SCR1_RVE_EXT
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`define SCR1_MPRF_AWIDTH 5
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`define SCR1_MPRF_AWIDTH 5
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`define SCR1_MPRF_SIZE 32
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`define SCR1_MPRF_SIZE 32
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`endif // SCR1_RVE_EXT
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`endif // SCR1_RVE_EXT
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typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v;
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// Masked due to iverilog issue
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typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v;
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//typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v;
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//typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v;
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parameter int unsigned SCR1_CSR_ADDR_WIDTH = 12;
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parameter int unsigned SCR1_CSR_ADDR_WIDTH = 12;
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parameter int unsigned SCR1_CSR_MTVEC_BASE_ZERO_BITS = 6;
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parameter int unsigned SCR1_CSR_MTVEC_BASE_ZERO_BITS = 6;
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parameter int unsigned SCR1_CSR_MTVEC_BASE_VAL_BITS = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;
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parameter int unsigned SCR1_CSR_MTVEC_BASE_VAL_BITS = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;
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parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_WR_RST_VAL =
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parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_WR_RST_VAL =
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SCR1_CSR_MTVEC_BASE_VAL_BITS'(SCR1_ARCH_MTVEC_BASE >> SCR1_CSR_MTVEC_BASE_ZERO_BITS);
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SCR1_CSR_MTVEC_BASE_VAL_BITS'(SCR1_ARCH_MTVEC_BASE >> SCR1_CSR_MTVEC_BASE_ZERO_BITS);
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parameter int unsigned SCR1_CSR_MTVEC_BASE_RO_BITS = (`SCR1_XLEN-(SCR1_CSR_MTVEC_BASE_ZERO_BITS+SCR1_MTVEC_BASE_WR_BITS));
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parameter int unsigned SCR1_CSR_MTVEC_BASE_RO_BITS = (`SCR1_XLEN-(SCR1_CSR_MTVEC_BASE_ZERO_BITS+SCR1_MTVEC_BASE_WR_BITS));
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`define SCR1_MTVAL_ILLEGAL_INSTR_EN
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`define SCR1_MTVAL_ILLEGAL_INSTR_EN
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Exception and IRQ codes
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// Exception and IRQ codes
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4;
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parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4;
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// Exceptions
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// Exceptions
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typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] {
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typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] {
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SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU
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SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU
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SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU
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SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU
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SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR
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SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR
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SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM
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SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM
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SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU
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SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU
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SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU
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SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU
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SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU
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SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU
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SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU
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SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU
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SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU
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SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU
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} type_scr1_exc_code_e;
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} type_scr1_exc_code_e;
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// IRQs, reset
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// IRQs, reset
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0;
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parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Operand width for BRKM
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// Operand width for BRKM
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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typedef enum logic [1:0] {
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typedef enum logic [1:0] {
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SCR1_OP_WIDTH_BYTE = 2'b00,
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SCR1_OP_WIDTH_BYTE = 2'b00,
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SCR1_OP_WIDTH_HALF = 2'b01,
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SCR1_OP_WIDTH_HALF = 2'b01,
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SCR1_OP_WIDTH_WORD = 2'b10
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SCR1_OP_WIDTH_WORD = 2'b10
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`ifdef SCR1_XPROP_EN
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`ifdef SCR1_XPROP_EN
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,
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,
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SCR1_OP_WIDTH_ERROR = 'x
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SCR1_OP_WIDTH_ERROR = 'x
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`endif // SCR1_XPROP_EN
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`endif // SCR1_XPROP_EN
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} type_scr1_op_width_e;
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} type_scr1_op_width_e;
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`endif //SCR1_ARCH_TYPES_SVH
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`endif //SCR1_ARCH_TYPES_SVH
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