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`include "scr1_arch_types.svh"
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`include "scr1_arch_types.svh"
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Instruction types
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// Instruction types
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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typedef enum logic [1:0] {
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//typedef enum logic [1:0] {
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SCR1_INSTR_RVC0 = 2'b00,
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parameter SCR1_INSTR_RVC0 = 2'b00;
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SCR1_INSTR_RVC1 = 2'b01,
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parameter SCR1_INSTR_RVC1 = 2'b01;
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SCR1_INSTR_RVC2 = 2'b10,
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parameter SCR1_INSTR_RVC2 = 2'b10;
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SCR1_INSTR_RVI = 2'b11
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parameter SCR1_INSTR_RVI = 2'b11;
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} type_scr1_instr_type_e;
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//} type_scr1_instr_type_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// RV32I opcodes (bits 6:2)
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// RV32I opcodes (bits 6:2)
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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typedef enum logic [6:2] {
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//typedef enum logic [6:2] {
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SCR1_OPCODE_LOAD = 5'b00000,
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parameter SCR1_OPCODE_LOAD = 5'b00000;
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SCR1_OPCODE_MISC_MEM = 5'b00011,
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parameter SCR1_OPCODE_MISC_MEM = 5'b00011;
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SCR1_OPCODE_OP_IMM = 5'b00100,
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parameter SCR1_OPCODE_OP_IMM = 5'b00100;
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SCR1_OPCODE_AUIPC = 5'b00101,
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parameter SCR1_OPCODE_AUIPC = 5'b00101;
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SCR1_OPCODE_STORE = 5'b01000,
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parameter SCR1_OPCODE_STORE = 5'b01000;
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SCR1_OPCODE_OP = 5'b01100,
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parameter SCR1_OPCODE_OP = 5'b01100;
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SCR1_OPCODE_LUI = 5'b01101,
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parameter SCR1_OPCODE_LUI = 5'b01101;
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SCR1_OPCODE_BRANCH = 5'b11000,
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parameter SCR1_OPCODE_BRANCH = 5'b11000;
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SCR1_OPCODE_JALR = 5'b11001,
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parameter SCR1_OPCODE_JALR = 5'b11001;
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SCR1_OPCODE_JAL = 5'b11011,
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parameter SCR1_OPCODE_JAL = 5'b11011;
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SCR1_OPCODE_SYSTEM = 5'b11100
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parameter SCR1_OPCODE_SYSTEM = 5'b11100;
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} type_scr1_rvi_opcode_e;
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//} type_scr1_rvi_opcode_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// IALU main operands
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// IALU main operands
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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