/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @file
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/// @brief RISC-V ISA definitions file
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/// @brief RISC-V ISA definitions file
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///
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///
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`ifndef SCR1_RISCV_ISA_DECODING_SVH
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`ifndef SCR1_RISCV_ISA_DECODING_SVH
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`define SCR1_RISCV_ISA_DECODING_SVH
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`define SCR1_RISCV_ISA_DECODING_SVH
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`include "scr1_arch_description.svh"
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`include "scr1_arch_description.svh"
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`include "scr1_arch_types.svh"
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`include "scr1_arch_types.svh"
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Instruction types
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// Instruction types
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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typedef enum logic [1:0] {
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//typedef enum logic [1:0] {
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SCR1_INSTR_RVC0 = 2'b00,
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parameter SCR1_INSTR_RVC0 = 2'b00;
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SCR1_INSTR_RVC1 = 2'b01,
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parameter SCR1_INSTR_RVC1 = 2'b01;
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SCR1_INSTR_RVC2 = 2'b10,
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parameter SCR1_INSTR_RVC2 = 2'b10;
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SCR1_INSTR_RVI = 2'b11
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parameter SCR1_INSTR_RVI = 2'b11;
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} type_scr1_instr_type_e;
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//} type_scr1_instr_type_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// RV32I opcodes (bits 6:2)
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// RV32I opcodes (bits 6:2)
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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typedef enum logic [6:2] {
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//typedef enum logic [6:2] {
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SCR1_OPCODE_LOAD = 5'b00000,
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parameter SCR1_OPCODE_LOAD = 5'b00000;
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SCR1_OPCODE_MISC_MEM = 5'b00011,
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parameter SCR1_OPCODE_MISC_MEM = 5'b00011;
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SCR1_OPCODE_OP_IMM = 5'b00100,
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parameter SCR1_OPCODE_OP_IMM = 5'b00100;
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SCR1_OPCODE_AUIPC = 5'b00101,
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parameter SCR1_OPCODE_AUIPC = 5'b00101;
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SCR1_OPCODE_STORE = 5'b01000,
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parameter SCR1_OPCODE_STORE = 5'b01000;
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SCR1_OPCODE_OP = 5'b01100,
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parameter SCR1_OPCODE_OP = 5'b01100;
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SCR1_OPCODE_LUI = 5'b01101,
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parameter SCR1_OPCODE_LUI = 5'b01101;
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SCR1_OPCODE_BRANCH = 5'b11000,
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parameter SCR1_OPCODE_BRANCH = 5'b11000;
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SCR1_OPCODE_JALR = 5'b11001,
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parameter SCR1_OPCODE_JALR = 5'b11001;
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SCR1_OPCODE_JAL = 5'b11011,
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parameter SCR1_OPCODE_JAL = 5'b11011;
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SCR1_OPCODE_SYSTEM = 5'b11100
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parameter SCR1_OPCODE_SYSTEM = 5'b11100;
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} type_scr1_rvi_opcode_e;
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//} type_scr1_rvi_opcode_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// IALU main operands
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// IALU main operands
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_IALU_OP_ALL_NUM_E = 2;
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localparam SCR1_IALU_OP_ALL_NUM_E = 2;
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localparam SCR1_IALU_OP_WIDTH_E = $clog2(SCR1_IALU_OP_ALL_NUM_E);
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localparam SCR1_IALU_OP_WIDTH_E = $clog2(SCR1_IALU_OP_ALL_NUM_E);
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typedef enum logic [SCR1_IALU_OP_WIDTH_E-1:0] {
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typedef enum logic [SCR1_IALU_OP_WIDTH_E-1:0] {
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SCR1_IALU_OP_REG_IMM, // op1 = rs1; op2 = imm
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SCR1_IALU_OP_REG_IMM, // op1 = rs1; op2 = imm
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SCR1_IALU_OP_REG_REG // op1 = rs1; op2 = rs2
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SCR1_IALU_OP_REG_REG // op1 = rs1; op2 = rs2
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} type_scr1_ialu_op_sel_e;
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} type_scr1_ialu_op_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// IALU main commands
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// IALU main commands
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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`ifdef SCR1_RVM_EXT
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`ifdef SCR1_RVM_EXT
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localparam SCR1_IALU_CMD_ALL_NUM_E = 23;
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localparam SCR1_IALU_CMD_ALL_NUM_E = 23;
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`else // ~SCR1_RVM_EXT
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`else // ~SCR1_RVM_EXT
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localparam SCR1_IALU_CMD_ALL_NUM_E = 15;
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localparam SCR1_IALU_CMD_ALL_NUM_E = 15;
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`endif // ~SCR1_RVM_EXT
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`endif // ~SCR1_RVM_EXT
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localparam SCR1_IALU_CMD_WIDTH_E = $clog2(SCR1_IALU_CMD_ALL_NUM_E);
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localparam SCR1_IALU_CMD_WIDTH_E = $clog2(SCR1_IALU_CMD_ALL_NUM_E);
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typedef enum logic [SCR1_IALU_CMD_WIDTH_E-1:0] {
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typedef enum logic [SCR1_IALU_CMD_WIDTH_E-1:0] {
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SCR1_IALU_CMD_NONE = '0, // IALU disable
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SCR1_IALU_CMD_NONE = '0, // IALU disable
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SCR1_IALU_CMD_AND, // op1 & op2
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SCR1_IALU_CMD_AND, // op1 & op2
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SCR1_IALU_CMD_OR, // op1 | op2
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SCR1_IALU_CMD_OR, // op1 | op2
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SCR1_IALU_CMD_XOR, // op1 ^ op2
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SCR1_IALU_CMD_XOR, // op1 ^ op2
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SCR1_IALU_CMD_ADD, // op1 + op2
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SCR1_IALU_CMD_ADD, // op1 + op2
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SCR1_IALU_CMD_SUB, // op1 - op2
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SCR1_IALU_CMD_SUB, // op1 - op2
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SCR1_IALU_CMD_SUB_LT, // op1 < op2
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SCR1_IALU_CMD_SUB_LT, // op1 < op2
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SCR1_IALU_CMD_SUB_LTU, // op1 u< op2
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SCR1_IALU_CMD_SUB_LTU, // op1 u< op2
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SCR1_IALU_CMD_SUB_EQ, // op1 = op2
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SCR1_IALU_CMD_SUB_EQ, // op1 = op2
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SCR1_IALU_CMD_SUB_NE, // op1 != op2
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SCR1_IALU_CMD_SUB_NE, // op1 != op2
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SCR1_IALU_CMD_SUB_GE, // op1 >= op2
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SCR1_IALU_CMD_SUB_GE, // op1 >= op2
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SCR1_IALU_CMD_SUB_GEU, // op1 u>= op2
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SCR1_IALU_CMD_SUB_GEU, // op1 u>= op2
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SCR1_IALU_CMD_SLL, // op1 << op2
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SCR1_IALU_CMD_SLL, // op1 << op2
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SCR1_IALU_CMD_SRL, // op1 >> op2
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SCR1_IALU_CMD_SRL, // op1 >> op2
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SCR1_IALU_CMD_SRA // op1 >>> op2
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SCR1_IALU_CMD_SRA // op1 >>> op2
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`ifdef SCR1_RVM_EXT
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`ifdef SCR1_RVM_EXT
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,
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,
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SCR1_IALU_CMD_MUL, // low(unsig(op1) * unsig(op2))
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SCR1_IALU_CMD_MUL, // low(unsig(op1) * unsig(op2))
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SCR1_IALU_CMD_MULHU, // high(unsig(op1) * unsig(op2))
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SCR1_IALU_CMD_MULHU, // high(unsig(op1) * unsig(op2))
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SCR1_IALU_CMD_MULHSU, // high(op1 * unsig(op2))
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SCR1_IALU_CMD_MULHSU, // high(op1 * unsig(op2))
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SCR1_IALU_CMD_MULH, // high(op1 * op2)
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SCR1_IALU_CMD_MULH, // high(op1 * op2)
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SCR1_IALU_CMD_DIV, // op1 / op2
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SCR1_IALU_CMD_DIV, // op1 / op2
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SCR1_IALU_CMD_DIVU, // op1 u/ op2
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SCR1_IALU_CMD_DIVU, // op1 u/ op2
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SCR1_IALU_CMD_REM, // op1 % op2
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SCR1_IALU_CMD_REM, // op1 % op2
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SCR1_IALU_CMD_REMU // op1 u% op2
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SCR1_IALU_CMD_REMU // op1 u% op2
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`endif // SCR1_RVM_EXT
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`endif // SCR1_RVM_EXT
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} type_scr1_ialu_cmd_sel_e;
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} type_scr1_ialu_cmd_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// IALU SUM2 operands (result is JUMP/BRANCH target, LOAD/STORE address)
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// IALU SUM2 operands (result is JUMP/BRANCH target, LOAD/STORE address)
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_SUM2_OP_ALL_NUM_E = 2;
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localparam SCR1_SUM2_OP_ALL_NUM_E = 2;
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localparam SCR1_SUM2_OP_WIDTH_E = $clog2(SCR1_SUM2_OP_ALL_NUM_E);
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localparam SCR1_SUM2_OP_WIDTH_E = $clog2(SCR1_SUM2_OP_ALL_NUM_E);
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typedef enum logic [SCR1_SUM2_OP_WIDTH_E-1:0] {
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typedef enum logic [SCR1_SUM2_OP_WIDTH_E-1:0] {
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SCR1_SUM2_OP_PC_IMM, // op1 = curr_pc; op2 = imm (AUIPC, target new_pc for JAL and branches)
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SCR1_SUM2_OP_PC_IMM, // op1 = curr_pc; op2 = imm (AUIPC, target new_pc for JAL and branches)
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SCR1_SUM2_OP_REG_IMM // op1 = rs1; op2 = imm (target new_pc for JALR, LOAD/STORE address)
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SCR1_SUM2_OP_REG_IMM // op1 = rs1; op2 = imm (target new_pc for JALR, LOAD/STORE address)
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`ifdef SCR1_XPROP_EN
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`ifdef SCR1_XPROP_EN
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,
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,
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SCR1_SUM2_OP_ERROR = 'x
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SCR1_SUM2_OP_ERROR = 'x
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`endif // SCR1_XPROP_EN
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`endif // SCR1_XPROP_EN
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} type_scr1_ialu_sum2_op_sel_e;
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} type_scr1_ialu_sum2_op_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// LSU commands
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// LSU commands
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_LSU_CMD_ALL_NUM_E = 9;
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localparam SCR1_LSU_CMD_ALL_NUM_E = 9;
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localparam SCR1_LSU_CMD_WIDTH_E = $clog2(SCR1_LSU_CMD_ALL_NUM_E);
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localparam SCR1_LSU_CMD_WIDTH_E = $clog2(SCR1_LSU_CMD_ALL_NUM_E);
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typedef enum logic [SCR1_LSU_CMD_WIDTH_E-1:0] {
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typedef enum logic [SCR1_LSU_CMD_WIDTH_E-1:0] {
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SCR1_LSU_CMD_NONE = '0,
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SCR1_LSU_CMD_NONE = '0,
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SCR1_LSU_CMD_LB,
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SCR1_LSU_CMD_LB,
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SCR1_LSU_CMD_LH,
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SCR1_LSU_CMD_LH,
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SCR1_LSU_CMD_LW,
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SCR1_LSU_CMD_LW,
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SCR1_LSU_CMD_LBU,
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SCR1_LSU_CMD_LBU,
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SCR1_LSU_CMD_LHU,
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SCR1_LSU_CMD_LHU,
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SCR1_LSU_CMD_SB,
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SCR1_LSU_CMD_SB,
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SCR1_LSU_CMD_SH,
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SCR1_LSU_CMD_SH,
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SCR1_LSU_CMD_SW
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SCR1_LSU_CMD_SW
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} type_scr1_lsu_cmd_sel_e;
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} type_scr1_lsu_cmd_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// CSR operands
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// CSR operands
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_CSR_OP_ALL_NUM_E = 2;
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localparam SCR1_CSR_OP_ALL_NUM_E = 2;
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localparam SCR1_CSR_OP_WIDTH_E = $clog2(SCR1_CSR_OP_ALL_NUM_E);
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localparam SCR1_CSR_OP_WIDTH_E = $clog2(SCR1_CSR_OP_ALL_NUM_E);
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typedef enum logic [SCR1_CSR_OP_WIDTH_E-1:0] {
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typedef enum logic [SCR1_CSR_OP_WIDTH_E-1:0] {
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SCR1_CSR_OP_IMM,
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SCR1_CSR_OP_IMM,
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SCR1_CSR_OP_REG
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SCR1_CSR_OP_REG
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} type_scr1_csr_op_sel_e;
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} type_scr1_csr_op_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// CSR commands
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// CSR commands
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_CSR_CMD_ALL_NUM_E = 4;
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localparam SCR1_CSR_CMD_ALL_NUM_E = 4;
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localparam SCR1_CSR_CMD_WIDTH_E = $clog2(SCR1_CSR_CMD_ALL_NUM_E);
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localparam SCR1_CSR_CMD_WIDTH_E = $clog2(SCR1_CSR_CMD_ALL_NUM_E);
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typedef enum logic [SCR1_CSR_CMD_WIDTH_E-1:0] {
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typedef enum logic [SCR1_CSR_CMD_WIDTH_E-1:0] {
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SCR1_CSR_CMD_NONE = '0,
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SCR1_CSR_CMD_NONE = '0,
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SCR1_CSR_CMD_WRITE,
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SCR1_CSR_CMD_WRITE,
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SCR1_CSR_CMD_SET,
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SCR1_CSR_CMD_SET,
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SCR1_CSR_CMD_CLEAR
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SCR1_CSR_CMD_CLEAR
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} type_scr1_csr_cmd_sel_e;
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} type_scr1_csr_cmd_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// MPRF rd writeback source
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// MPRF rd writeback source
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_RD_WB_ALL_NUM_E = 7;
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localparam SCR1_RD_WB_ALL_NUM_E = 7;
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localparam SCR1_RD_WB_WIDTH_E = $clog2(SCR1_RD_WB_ALL_NUM_E);
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localparam SCR1_RD_WB_WIDTH_E = $clog2(SCR1_RD_WB_ALL_NUM_E);
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typedef enum logic [SCR1_RD_WB_WIDTH_E-1:0] {
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typedef enum logic [SCR1_RD_WB_WIDTH_E-1:0] {
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SCR1_RD_WB_NONE = '0,
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SCR1_RD_WB_NONE = '0,
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SCR1_RD_WB_IALU, // IALU main result
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SCR1_RD_WB_IALU, // IALU main result
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SCR1_RD_WB_SUM2, // IALU SUM2 result (AUIPC)
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SCR1_RD_WB_SUM2, // IALU SUM2 result (AUIPC)
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SCR1_RD_WB_IMM, // LUI
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SCR1_RD_WB_IMM, // LUI
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SCR1_RD_WB_INC_PC, // JAL(R)
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SCR1_RD_WB_INC_PC, // JAL(R)
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SCR1_RD_WB_LSU, // Load from DMEM
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SCR1_RD_WB_LSU, // Load from DMEM
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SCR1_RD_WB_CSR // Read CSR
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SCR1_RD_WB_CSR // Read CSR
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} type_scr1_rd_wb_sel_e;
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} type_scr1_rd_wb_sel_e;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// IDU to EXU full command structure
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// IDU to EXU full command structure
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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localparam SCR1_GPR_FIELD_WIDTH = 5;
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localparam SCR1_GPR_FIELD_WIDTH = 5;
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typedef struct packed {
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typedef struct packed {
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logic instr_rvc; // used with a different meaning for IFU access fault exception
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logic instr_rvc; // used with a different meaning for IFU access fault exception
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type_scr1_ialu_op_sel_e ialu_op;
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type_scr1_ialu_op_sel_e ialu_op;
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type_scr1_ialu_cmd_sel_e ialu_cmd;
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type_scr1_ialu_cmd_sel_e ialu_cmd;
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type_scr1_ialu_sum2_op_sel_e sum2_op;
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type_scr1_ialu_sum2_op_sel_e sum2_op;
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type_scr1_lsu_cmd_sel_e lsu_cmd;
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type_scr1_lsu_cmd_sel_e lsu_cmd;
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type_scr1_csr_op_sel_e csr_op;
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type_scr1_csr_op_sel_e csr_op;
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type_scr1_csr_cmd_sel_e csr_cmd;
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type_scr1_csr_cmd_sel_e csr_cmd;
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type_scr1_rd_wb_sel_e rd_wb_sel;
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type_scr1_rd_wb_sel_e rd_wb_sel;
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logic jump_req;
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logic jump_req;
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logic branch_req;
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logic branch_req;
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logic mret_req;
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logic mret_req;
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logic fencei_req;
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logic fencei_req;
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logic wfi_req;
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logic wfi_req;
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logic [SCR1_GPR_FIELD_WIDTH-1:0] rs1_addr; // also used as zimm for CSRRxI instructions
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logic [SCR1_GPR_FIELD_WIDTH-1:0] rs1_addr; // also used as zimm for CSRRxI instructions
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logic [SCR1_GPR_FIELD_WIDTH-1:0] rs2_addr;
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logic [SCR1_GPR_FIELD_WIDTH-1:0] rs2_addr;
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logic [SCR1_GPR_FIELD_WIDTH-1:0] rd_addr;
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logic [SCR1_GPR_FIELD_WIDTH-1:0] rd_addr;
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logic [`SCR1_XLEN-1:0] imm; // used as {funct3, CSR address} for CSR instructions
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logic [`SCR1_XLEN-1:0] imm; // used as {funct3, CSR address} for CSR instructions
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// used as instruction field for illegal instruction exception
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// used as instruction field for illegal instruction exception
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logic exc_req;
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logic exc_req;
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type_scr1_exc_code_e exc_code;
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type_scr1_exc_code_e exc_code;
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} type_scr1_exu_cmd_s;
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} type_scr1_exu_cmd_s;
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`endif // SCR1_RISCV_ISA_DECODING_SVH
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`endif // SCR1_RISCV_ISA_DECODING_SVH
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