| Line 18... |
Line 18... |
input logic clk,
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input logic clk,
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// Core interface
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// Core interface
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output logic dmem_req_ack,
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output logic dmem_req_ack,
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input logic dmem_req,
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input logic dmem_req,
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input type_scr1_mem_cmd_e dmem_cmd,
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input logic dmem_cmd,
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input type_scr1_mem_width_e dmem_width,
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input logic [1:0] dmem_width,
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input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
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input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
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output type_scr1_mem_resp_e dmem_resp,
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output logic [1:0] dmem_resp,
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// PORT0 interface
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// PORT0 interface
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input logic port0_req_ack,
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input logic port0_req_ack,
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output logic port0_req,
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output logic port0_req,
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output type_scr1_mem_cmd_e port0_cmd,
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output logic port0_cmd,
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output type_scr1_mem_width_e port0_width,
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output logic [1:0] port0_width,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port0_addr,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port0_addr,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port0_wdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port0_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port0_rdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port0_rdata,
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input type_scr1_mem_resp_e port0_resp,
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input logic [1:0] port0_resp,
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// PORT1 interface
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// PORT1 interface
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input logic port1_req_ack,
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input logic port1_req_ack,
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output logic port1_req,
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output logic port1_req,
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output type_scr1_mem_cmd_e port1_cmd,
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output logic port1_cmd,
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output type_scr1_mem_width_e port1_width,
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output logic [1:0] port1_width,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port1_addr,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port1_addr,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port1_wdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port1_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port1_rdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port1_rdata,
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input type_scr1_mem_resp_e port1_resp,
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input logic [1:0] port1_resp,
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// PORT2 interface
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// PORT2 interface
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input logic port2_req_ack,
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input logic port2_req_ack,
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output logic port2_req,
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output logic port2_req,
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output type_scr1_mem_cmd_e port2_cmd,
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output logic port2_cmd,
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output type_scr1_mem_width_e port2_width,
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output logic [1:0] port2_width,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port2_addr,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port2_addr,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port2_wdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port2_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port2_rdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port2_rdata,
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input type_scr1_mem_resp_e port2_resp
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input logic [1:0] port2_resp
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);
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);
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local types declaration
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// Local types declaration
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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| Line 77... |
Line 77... |
//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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type_scr1_fsm_e fsm;
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type_scr1_fsm_e fsm;
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type_scr1_sel_e port_sel;
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type_scr1_sel_e port_sel;
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type_scr1_sel_e port_sel_r;
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type_scr1_sel_e port_sel_r;
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logic [`SCR1_DMEM_DWIDTH-1:0] sel_rdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] sel_rdata;
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type_scr1_mem_resp_e sel_resp;
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logic [1:0] sel_resp;
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logic sel_req_ack;
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logic sel_req_ack;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// FSM
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// FSM
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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