URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_dmem_wb.sv] - Diff between revs 19 and 20

Rev 19	Rev 20
Line 335...	Line 335...
`endcase`	`endcase`
`end`	`end`


`wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};`	`wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};`
	`wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_dout;`

`sync_fifo #(`	`sync_fifo #(`
`.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width`	`.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width`
`.D(2) // FIFO DEPTH`	`.D(2) // FIFO DEPTH`
`) u_req_fifo(`	`) u_req_fifo(`
Line 361...	Line 362...
`wire [2:0] hwidth_out;`	`wire [2:0] hwidth_out;`
`wire [SCR1_WB_WIDTH-1:0] haddr_out;`	`wire [SCR1_WB_WIDTH-1:0] haddr_out;`
`wire [SCR1_WB_WIDTH-1:0] hwdata_out;`	`wire [SCR1_WB_WIDTH-1:0] hwdata_out;`
`wire [3:0] hbel_out;`	`wire [3:0] hbel_out;`


`assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout;`	`assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout;`

`always_ff @(posedge clk) begin`	`always_ff @(posedge clk) begin`
`if (wbd_ack_i) begin`	`if (wbd_ack_i) begin`
`if (~req_fifo_empty) begin`	`if (~req_fifo_empty) begin`