//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// yifive Wishbone interface for Data memory ////
|
//// yifive Wishbone interface for Data memory ////
|
//// ////
|
//// ////
|
//// This file is part of the yifive cores project ////
|
//// This file is part of the yifive cores project ////
|
//// http://www.opencores.org/cores/yifive/ ////
|
//// http://www.opencores.org/cores/yifive/ ////
|
//// ////
|
//// ////
|
//// Description: ////
|
//// Description: ////
|
//// integrated wishbone i/f to data memory ////
|
//// integrated wishbone i/f to data memory ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
//// Revision : ////
|
//// Revision : ////
|
//// v0: June 7, 2021, Dinesh A ////
|
//// v0: June 7, 2021, Dinesh A ////
|
//// wishbone integration ////
|
//// wishbone integration ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// Orginal owner Details ////
|
// Orginal owner Details ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
|
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
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/// @file ///
|
/// @file ///
|
/// @brief Data memory WB bridge ///
|
/// @brief Data memory WB bridge ///
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
`include "scr1_wb.svh"
|
`include "scr1_wb.svh"
|
`include "scr1_memif.svh"
|
`include "scr1_memif.svh"
|
|
|
module scr1_dmem_wb (
|
module scr1_dmem_wb (
|
// Control Signals
|
// Control Signals
|
input logic rst_n,
|
input logic rst_n,
|
input logic clk,
|
input logic clk,
|
|
|
// Core Interface
|
// Core Interface
|
output logic dmem_req_ack,
|
output logic dmem_req_ack,
|
input logic dmem_req,
|
input logic dmem_req,
|
input type_scr1_mem_cmd_e dmem_cmd,
|
input type_scr1_mem_cmd_e dmem_cmd,
|
input type_scr1_mem_width_e dmem_width,
|
input type_scr1_mem_width_e dmem_width,
|
input logic [SCR1_WB_WIDTH-1:0] dmem_addr,
|
input logic [SCR1_WB_WIDTH-1:0] dmem_addr,
|
input logic [SCR1_WB_WIDTH-1:0] dmem_wdata,
|
input logic [SCR1_WB_WIDTH-1:0] dmem_wdata,
|
output logic [SCR1_WB_WIDTH-1:0] dmem_rdata,
|
output logic [SCR1_WB_WIDTH-1:0] dmem_rdata,
|
output type_scr1_mem_resp_e dmem_resp,
|
output type_scr1_mem_resp_e dmem_resp,
|
|
|
// WB Interface
|
// WB Interface
|
output logic wbd_stb_o, // strobe/request
|
output logic wbd_stb_o, // strobe/request
|
output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
|
output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
|
output logic wbd_we_o, // write
|
output logic wbd_we_o, // write
|
output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
|
output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
|
output logic [3:0] wbd_sel_o, // byte enable
|
output logic [3:0] wbd_sel_o, // byte enable
|
input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
|
input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
|
input logic wbd_ack_i, // acknowlegement
|
input logic wbd_ack_i, // acknowlegement
|
input logic wbd_err_i // error
|
input logic wbd_err_i // error
|
|
|
);
|
);
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Local Parameters
|
// Local Parameters
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
`ifndef SCR1_DMEM_WB_OUT_BP
|
`ifndef SCR1_DMEM_WB_OUT_BP
|
localparam SCR1_FIFO_WIDTH = 2;
|
localparam SCR1_FIFO_WIDTH = 2;
|
localparam SCR1_FIFO_CNT_WIDTH = 2;
|
localparam SCR1_FIFO_CNT_WIDTH = 2;
|
`endif // SCR1_DMEM_WB_OUT_BP
|
`endif // SCR1_DMEM_WB_OUT_BP
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Local type declaration
|
// Local type declaration
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
typedef enum logic {
|
typedef enum logic {
|
SCR1_FSM_ADDR = 1'b0,
|
SCR1_FSM_ADDR = 1'b0,
|
SCR1_FSM_DATA = 1'b1,
|
SCR1_FSM_DATA = 1'b1,
|
SCR1_FSM_ERR = 1'bx
|
SCR1_FSM_ERR = 1'bx
|
} type_scr1_fsm_e;
|
} type_scr1_fsm_e;
|
|
|
typedef struct packed {
|
typedef struct packed {
|
logic hwrite;
|
logic hwrite;
|
logic [2:0] hwidth;
|
logic [2:0] hwidth;
|
logic [SCR1_WB_WIDTH-1:0] haddr;
|
logic [SCR1_WB_WIDTH-1:0] haddr;
|
logic [SCR1_WB_WIDTH-1:0] hwdata;
|
logic [SCR1_WB_WIDTH-1:0] hwdata;
|
} type_scr1_req_fifo_s;
|
} type_scr1_req_fifo_s;
|
|
|
typedef struct packed {
|
typedef struct packed {
|
logic hwrite;
|
logic hwrite;
|
logic [2:0] hwidth;
|
logic [2:0] hwidth;
|
logic [1:0] haddr;
|
logic [1:0] haddr;
|
} type_scr1_data_fifo_s;
|
} type_scr1_data_fifo_s;
|
|
|
typedef struct packed {
|
typedef struct packed {
|
logic hresp;
|
logic hresp;
|
logic [2:0] hwidth;
|
logic [2:0] hwidth;
|
logic [1:0] haddr;
|
logic [1:0] haddr;
|
logic [SCR1_WB_WIDTH-1:0] hrdata;
|
logic [SCR1_WB_WIDTH-1:0] hrdata;
|
} type_scr1_resp_fifo_s;
|
} type_scr1_resp_fifo_s;
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Local functions
|
// Local functions
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
function automatic logic [2:0] scr1_conv_mem2wb_width (
|
function automatic logic [2:0] scr1_conv_mem2wb_width (
|
input type_scr1_mem_width_e dmem_width
|
input type_scr1_mem_width_e dmem_width
|
);
|
);
|
logic [2:0] tmp;
|
logic [2:0] tmp;
|
begin
|
begin
|
case (dmem_width)
|
case (dmem_width)
|
SCR1_MEM_WIDTH_BYTE : begin
|
SCR1_MEM_WIDTH_BYTE : begin
|
tmp = SCR1_DSIZE_8B;
|
tmp = SCR1_DSIZE_8B;
|
end
|
end
|
SCR1_MEM_WIDTH_HWORD : begin
|
SCR1_MEM_WIDTH_HWORD : begin
|
tmp = SCR1_DSIZE_16B;
|
tmp = SCR1_DSIZE_16B;
|
end
|
end
|
SCR1_MEM_WIDTH_WORD : begin
|
SCR1_MEM_WIDTH_WORD : begin
|
tmp = SCR1_DSIZE_32B;
|
tmp = SCR1_DSIZE_32B;
|
end
|
end
|
default : begin
|
default : begin
|
tmp = SCR1_DSIZE_32B;
|
tmp = SCR1_DSIZE_32B;
|
end
|
end
|
endcase
|
endcase
|
scr1_conv_mem2wb_width = tmp; // cp.11
|
scr1_conv_mem2wb_width = tmp; // cp.11
|
end
|
end
|
endfunction
|
endfunction
|
|
|
function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
|
function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
|
input logic [1:0] dmem_addr,
|
input logic [1:0] dmem_addr,
|
input type_scr1_mem_width_e dmem_width,
|
input type_scr1_mem_width_e dmem_width,
|
input logic [SCR1_WB_WIDTH-1:0] dmem_wdata
|
input logic [SCR1_WB_WIDTH-1:0] dmem_wdata
|
);
|
);
|
logic [SCR1_WB_WIDTH-1:0] tmp;
|
logic [SCR1_WB_WIDTH-1:0] tmp;
|
begin
|
begin
|
tmp = 'x;
|
tmp = 'x;
|
case (dmem_width)
|
case (dmem_width)
|
SCR1_MEM_WIDTH_BYTE : begin
|
SCR1_MEM_WIDTH_BYTE : begin
|
case (dmem_addr)
|
case (dmem_addr)
|
2'b00 : begin
|
2'b00 : begin
|
tmp[7:0] = dmem_wdata[7:0];
|
tmp[7:0] = dmem_wdata[7:0];
|
end
|
end
|
2'b01 : begin
|
2'b01 : begin
|
tmp[15:8] = dmem_wdata[7:0];
|
tmp[15:8] = dmem_wdata[7:0];
|
end
|
end
|
2'b10 : begin
|
2'b10 : begin
|
tmp[23:16] = dmem_wdata[7:0];
|
tmp[23:16] = dmem_wdata[7:0];
|
end
|
end
|
2'b11 : begin
|
2'b11 : begin
|
tmp[31:24] = dmem_wdata[7:0];
|
tmp[31:24] = dmem_wdata[7:0];
|
end
|
end
|
default : begin
|
default : begin
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
SCR1_MEM_WIDTH_HWORD : begin
|
SCR1_MEM_WIDTH_HWORD : begin
|
case (dmem_addr[1])
|
case (dmem_addr[1])
|
1'b0 : begin
|
1'b0 : begin
|
tmp[15:0] = dmem_wdata[15:0];
|
tmp[15:0] = dmem_wdata[15:0];
|
end
|
end
|
1'b1 : begin
|
1'b1 : begin
|
tmp[31:16] = dmem_wdata[15:0];
|
tmp[31:16] = dmem_wdata[15:0];
|
end
|
end
|
default : begin
|
default : begin
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
SCR1_MEM_WIDTH_WORD : begin
|
SCR1_MEM_WIDTH_WORD : begin
|
tmp = dmem_wdata;
|
tmp = dmem_wdata;
|
end
|
end
|
default : begin
|
default : begin
|
end
|
end
|
endcase
|
endcase
|
scr1_conv_mem2wb_wdata = tmp;
|
scr1_conv_mem2wb_wdata = tmp;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_wb2mem_rdata (
|
function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_wb2mem_rdata (
|
input logic [2:0] hwidth,
|
input logic [2:0] hwidth,
|
input logic [1:0] haddr,
|
input logic [1:0] haddr,
|
input logic [SCR1_WB_WIDTH-1:0] hrdata
|
input logic [SCR1_WB_WIDTH-1:0] hrdata
|
);
|
);
|
logic [SCR1_WB_WIDTH-1:0] tmp;
|
logic [SCR1_WB_WIDTH-1:0] tmp;
|
begin
|
begin
|
tmp = 'x;
|
tmp = 'x;
|
case (hwidth)
|
case (hwidth)
|
SCR1_DSIZE_8B : begin
|
SCR1_DSIZE_8B : begin
|
case (haddr)
|
case (haddr)
|
2'b00 : tmp[7:0] = hrdata[7:0];
|
2'b00 : tmp[7:0] = hrdata[7:0];
|
2'b01 : tmp[7:0] = hrdata[15:8];
|
2'b01 : tmp[7:0] = hrdata[15:8];
|
2'b10 : tmp[7:0] = hrdata[23:16];
|
2'b10 : tmp[7:0] = hrdata[23:16];
|
2'b11 : tmp[7:0] = hrdata[31:24];
|
2'b11 : tmp[7:0] = hrdata[31:24];
|
default : begin
|
default : begin
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
SCR1_DSIZE_16B : begin
|
SCR1_DSIZE_16B : begin
|
case (haddr[1])
|
case (haddr[1])
|
1'b0 : tmp[15:0] = hrdata[15:0];
|
1'b0 : tmp[15:0] = hrdata[15:0];
|
1'b1 : tmp[15:0] = hrdata[31:16];
|
1'b1 : tmp[15:0] = hrdata[31:16];
|
default : begin
|
default : begin
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
SCR1_DSIZE_32B : begin
|
SCR1_DSIZE_32B : begin
|
tmp = hrdata;
|
tmp = hrdata;
|
end
|
end
|
default : begin
|
default : begin
|
end
|
end
|
endcase
|
endcase
|
scr1_conv_wb2mem_rdata = tmp;
|
scr1_conv_wb2mem_rdata = tmp;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Local signal declaration
|
// Local signal declaration
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
logic req_fifo_rd;
|
logic req_fifo_rd;
|
logic req_fifo_wr;
|
logic req_fifo_wr;
|
logic req_fifo_up;
|
logic req_fifo_up;
|
`ifdef SCR1_DMEM_WB_OUT_BP
|
`ifdef SCR1_DMEM_WB_OUT_BP
|
type_scr1_req_fifo_s req_fifo_new;
|
type_scr1_req_fifo_s req_fifo_new;
|
type_scr1_req_fifo_s req_fifo_r;
|
type_scr1_req_fifo_s req_fifo_r;
|
type_scr1_req_fifo_s [0:0] req_fifo;
|
type_scr1_req_fifo_s [0:0] req_fifo;
|
`else // SCR1_DMEM_WB_OUT_BP
|
`else // SCR1_DMEM_WB_OUT_BP
|
type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
|
type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
|
type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
|
type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
|
logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
|
logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
|
logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
|
logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
|
`endif // SCR1_DMEM_WB_OUT_BP
|
`endif // SCR1_DMEM_WB_OUT_BP
|
logic req_fifo_empty;
|
logic req_fifo_empty;
|
logic req_fifo_full;
|
logic req_fifo_full;
|
|
|
type_scr1_data_fifo_s data_fifo;
|
type_scr1_data_fifo_s data_fifo;
|
type_scr1_resp_fifo_s resp_fifo;
|
type_scr1_resp_fifo_s resp_fifo;
|
logic resp_fifo_hready;
|
logic resp_fifo_hready;
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Interface to Core
|
// Interface to Core
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
assign dmem_req_ack = ~req_fifo_full;
|
assign dmem_req_ack = ~req_fifo_full;
|
assign req_fifo_wr = ~req_fifo_full & dmem_req;
|
assign req_fifo_wr = ~req_fifo_full & dmem_req;
|
|
|
assign dmem_rdata = scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
|
assign dmem_rdata = scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
|
|
|
assign dmem_resp = (resp_fifo_hready)
|
assign dmem_resp = (resp_fifo_hready)
|
? (resp_fifo.hresp == 1'b1)
|
? (resp_fifo.hresp == 1'b1)
|
? SCR1_MEM_RESP_RDY_OK
|
? SCR1_MEM_RESP_RDY_OK
|
: SCR1_MEM_RESP_RDY_ER
|
: SCR1_MEM_RESP_RDY_ER
|
: SCR1_MEM_RESP_NOTRDY ;
|
: SCR1_MEM_RESP_NOTRDY ;
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// REQ_FIFO
|
// REQ_FIFO
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
`ifdef SCR1_DMEM_WB_OUT_BP
|
`ifdef SCR1_DMEM_WB_OUT_BP
|
always_ff @(negedge rst_n, posedge clk) begin
|
always_ff @(negedge rst_n, posedge clk) begin
|
if (~rst_n) begin
|
if (~rst_n) begin
|
req_fifo_full <= 1'b0;
|
req_fifo_full <= 1'b0;
|
end else begin
|
end else begin
|
if (~req_fifo_full) begin
|
if (~req_fifo_full) begin
|
req_fifo_full <= dmem_req & ~req_fifo_rd;
|
req_fifo_full <= dmem_req & ~req_fifo_rd;
|
end else begin
|
end else begin
|
req_fifo_full <= ~req_fifo_rd;
|
req_fifo_full <= ~req_fifo_rd;
|
end
|
end
|
end
|
end
|
end
|
end
|
assign req_fifo_empty = ~(req_fifo_full | dmem_req);
|
assign req_fifo_empty = ~(req_fifo_full | dmem_req);
|
|
|
assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
|
assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
|
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
if (req_fifo_up) begin
|
if (req_fifo_up) begin
|
req_fifo_r <= req_fifo_new;
|
req_fifo_r <= req_fifo_new;
|
end
|
end
|
end
|
end
|
|
|
assign req_fifo_new.hwrite = dmem_req ? (dmem_cmd == SCR1_MEM_CMD_WR) : 1'b0;
|
assign req_fifo_new.hwrite = dmem_req ? (dmem_cmd == SCR1_MEM_CMD_WR) : 1'b0;
|
assign req_fifo_new.hwidth = dmem_req ? scr1_conv_mem2wb_width(dmem_width) : '0;
|
assign req_fifo_new.hwidth = dmem_req ? scr1_conv_mem2wb_width(dmem_width) : '0;
|
assign req_fifo_new.haddr = dmem_req ? dmem_addr : '0;
|
assign req_fifo_new.haddr = dmem_req ? dmem_addr : '0;
|
assign req_fifo_new.hwdata = (dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR))
|
assign req_fifo_new.hwdata = (dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR))
|
? scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata)
|
? scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata)
|
: '0;
|
: '0;
|
assign req_fifo[0] = (req_fifo_full) ? req_fifo_r: req_fifo_new;
|
assign req_fifo[0] = (req_fifo_full) ? req_fifo_r: req_fifo_new;
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Register Data from response path - Used by Read path logic
|
// Register Data from response path - Used by Read path logic
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
if (wbd_ack_i) begin
|
if (wbd_ack_i) begin
|
if (~req_fifo_empty) begin
|
if (~req_fifo_empty) begin
|
data_fifo.hwidth <= req_fifo[0].hwidth;
|
data_fifo.hwidth <= req_fifo[0].hwidth;
|
data_fifo.haddr <= req_fifo[0].haddr[1:0];
|
data_fifo.haddr <= req_fifo[0].haddr[1:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`else // SCR1_DMEM_WB_OUT_BP
|
`else // SCR1_DMEM_WB_OUT_BP
|
|
|
|
|
wire hwrite_in = (dmem_cmd == SCR1_MEM_CMD_WR);
|
wire hwrite_in = (dmem_cmd == SCR1_MEM_CMD_WR);
|
wire [2:0] hwidth_in = scr1_conv_mem2wb_width(dmem_width);
|
wire [2:0] hwidth_in = scr1_conv_mem2wb_width(dmem_width);
|
wire [SCR1_WB_WIDTH-1:0] haddr_in = dmem_addr;
|
wire [SCR1_WB_WIDTH-1:0] haddr_in = dmem_addr;
|
wire [SCR1_WB_WIDTH-1:0] hwdata_in = scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
|
wire [SCR1_WB_WIDTH-1:0] hwdata_in = scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
|
|
|
reg [3:0] hbel_in; // byte select
|
reg [3:0] hbel_in; // byte select
|
always_comb begin
|
always_comb begin
|
hbel_in = 0;
|
hbel_in = 0;
|
case (hwidth_in)
|
case (hwidth_in)
|
SCR1_DSIZE_8B : begin
|
SCR1_DSIZE_8B : begin
|
hbel_in = 4'b0001 << haddr_in[1:0];
|
hbel_in = 4'b0001 << haddr_in[1:0];
|
end
|
end
|
SCR1_DSIZE_16B : begin
|
SCR1_DSIZE_16B : begin
|
hbel_in = 4'b0011 << haddr_in[1:0];
|
hbel_in = 4'b0011 << haddr_in[1:0];
|
end
|
end
|
SCR1_DSIZE_32B : begin
|
SCR1_DSIZE_32B : begin
|
hbel_in = 4'b1111;
|
hbel_in = 4'b1111;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};
|
wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};
|
|
wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_dout;
|
|
|
sync_fifo #(
|
sync_fifo #(
|
.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width
|
.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width
|
.D(2) // FIFO DEPTH
|
.D(2) // FIFO DEPTH
|
) u_req_fifo(
|
) u_req_fifo(
|
|
|
.rd_data (req_fifo_dout ),
|
.rd_data (req_fifo_dout ),
|
|
|
.reset_n (rst_n ),
|
.reset_n (rst_n ),
|
.clk (clk ),
|
.clk (clk ),
|
.wr_en (req_fifo_wr ), // Write
|
.wr_en (req_fifo_wr ), // Write
|
.rd_en (req_fifo_rd ), // Read
|
.rd_en (req_fifo_rd ), // Read
|
.wr_data (req_fifo_din ),
|
.wr_data (req_fifo_din ),
|
.full (req_fifo_full ),
|
.full (req_fifo_full ),
|
.empty (req_fifo_empty )
|
.empty (req_fifo_empty )
|
);
|
);
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// Register Data from response path - Used by Read path logic
|
// Register Data from response path - Used by Read path logic
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
wire hwrite_out;
|
wire hwrite_out;
|
wire [2:0] hwidth_out;
|
wire [2:0] hwidth_out;
|
wire [SCR1_WB_WIDTH-1:0] haddr_out;
|
wire [SCR1_WB_WIDTH-1:0] haddr_out;
|
wire [SCR1_WB_WIDTH-1:0] hwdata_out;
|
wire [SCR1_WB_WIDTH-1:0] hwdata_out;
|
wire [3:0] hbel_out;
|
wire [3:0] hbel_out;
|
|
|
|
|
assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout;
|
assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout;
|
|
|
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
if (wbd_ack_i) begin
|
if (wbd_ack_i) begin
|
if (~req_fifo_empty) begin
|
if (~req_fifo_empty) begin
|
data_fifo.hwidth <= hwidth_out;
|
data_fifo.hwidth <= hwidth_out;
|
data_fifo.haddr <= haddr_out[1:0];
|
data_fifo.haddr <= haddr_out[1:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`endif // SCR1_DMEM_WB_OUT_BP
|
`endif // SCR1_DMEM_WB_OUT_BP
|
|
|
|
|
always_comb begin
|
always_comb begin
|
req_fifo_rd = 1'b0;
|
req_fifo_rd = 1'b0;
|
if (wbd_ack_i) begin
|
if (wbd_ack_i) begin
|
req_fifo_rd = ~req_fifo_empty;
|
req_fifo_rd = ~req_fifo_empty;
|
end
|
end
|
end
|
end
|
|
|
|
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
// FIFO response
|
// FIFO response
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
`ifdef SCR1_DMEM_WB_IN_BP
|
`ifdef SCR1_DMEM_WB_IN_BP
|
|
|
assign resp_fifo_hready = wbd_ack_i;
|
assign resp_fifo_hready = wbd_ack_i;
|
assign resp_fifo.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
|
assign resp_fifo.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
|
assign resp_fifo.hwidth = data_fifo.hwidth;
|
assign resp_fifo.hwidth = data_fifo.hwidth;
|
assign resp_fifo.haddr = data_fifo.haddr;
|
assign resp_fifo.haddr = data_fifo.haddr;
|
assign resp_fifo.hrdata = wbd_dat_i;
|
assign resp_fifo.hrdata = wbd_dat_i;
|
|
|
assign wbd_stb_o = ~req_fifo_empty;
|
assign wbd_stb_o = ~req_fifo_empty;
|
assign wbd_adr_o = req_fifo[0].haddr;
|
assign wbd_adr_o = req_fifo[0].haddr;
|
assign wbd_we_o = req_fifo[0].hwrite;
|
assign wbd_we_o = req_fifo[0].hwrite;
|
assign wbd_dat_o = req_fifo[0].hwdata;
|
assign wbd_dat_o = req_fifo[0].hwdata;
|
|
|
always_comb begin
|
always_comb begin
|
wbd_sel_o = 0;
|
wbd_sel_o = 0;
|
case (req_fifo[0].hwidth)
|
case (req_fifo[0].hwidth)
|
SCR1_DSIZE_8B : begin
|
SCR1_DSIZE_8B : begin
|
wbd_sel_o = 4'b0001 << req_fifo[0].haddr[1:0];
|
wbd_sel_o = 4'b0001 << req_fifo[0].haddr[1:0];
|
end
|
end
|
SCR1_DSIZE_16B : begin
|
SCR1_DSIZE_16B : begin
|
wbd_sel_o = 4'b0011 << req_fifo[0].haddr[1:0];
|
wbd_sel_o = 4'b0011 << req_fifo[0].haddr[1:0];
|
end
|
end
|
SCR1_DSIZE_32B : begin
|
SCR1_DSIZE_32B : begin
|
wbd_sel_o = 4'b1111;
|
wbd_sel_o = 4'b1111;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`else // SCR1_DMEM_WB_IN_BP
|
`else // SCR1_DMEM_WB_IN_BP
|
always_ff @(negedge rst_n, posedge clk) begin
|
always_ff @(negedge rst_n, posedge clk) begin
|
if (~rst_n) begin
|
if (~rst_n) begin
|
resp_fifo_hready <= 1'b0;
|
resp_fifo_hready <= 1'b0;
|
end else begin
|
end else begin
|
resp_fifo_hready <= wbd_ack_i ;
|
resp_fifo_hready <= wbd_ack_i ;
|
end
|
end
|
end
|
end
|
|
|
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
if (wbd_ack_i) begin
|
if (wbd_ack_i) begin
|
resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
|
resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
|
resp_fifo.hwidth <= data_fifo.hwidth;
|
resp_fifo.hwidth <= data_fifo.hwidth;
|
resp_fifo.haddr <= data_fifo.haddr;
|
resp_fifo.haddr <= data_fifo.haddr;
|
resp_fifo.hrdata <= wbd_dat_i;
|
resp_fifo.hrdata <= wbd_dat_i;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign wbd_stb_o = ~req_fifo_empty;
|
assign wbd_stb_o = ~req_fifo_empty;
|
assign wbd_adr_o = haddr_out;
|
assign wbd_adr_o = haddr_out;
|
assign wbd_we_o = hwrite_out;
|
assign wbd_we_o = hwrite_out;
|
assign wbd_dat_o = hwdata_out;
|
assign wbd_dat_o = hwdata_out;
|
assign wbd_sel_o = hbel_out;
|
assign wbd_sel_o = hbel_out;
|
|
|
`endif // SCR1_DMEM_WB_IN_BP
|
`endif // SCR1_DMEM_WB_IN_BP
|
|
|
|
|
|
|
endmodule : scr1_dmem_wb
|
endmodule : scr1_dmem_wb
|
|
|