| Line 15... |
Line 15... |
//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//// Revision : ////
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//// v0: June 7, 2021, Dinesh A ////
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//// v0: June 7, 2021, Dinesh A ////
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//// wishbone integration ////
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//// wishbone integration ////
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//// v1: June 9, 2021, Dinesh A ////
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//// On power up, wishbone output are unkown as it ////
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//// driven from fifo output. To avoid unknown ////
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//// propgation, we are driving 'h0 when fifo empty ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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| Line 60... |
Line 64... |
input logic clk,
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input logic clk,
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// Core Interface
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// Core Interface
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output logic dmem_req_ack,
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output logic dmem_req_ack,
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input logic dmem_req,
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input logic dmem_req,
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input type_scr1_mem_cmd_e dmem_cmd,
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input logic dmem_cmd,
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input type_scr1_mem_width_e dmem_width,
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input logic [1:0] dmem_width,
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input logic [SCR1_WB_WIDTH-1:0] dmem_addr,
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input logic [SCR1_WB_WIDTH-1:0] dmem_addr,
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input logic [SCR1_WB_WIDTH-1:0] dmem_wdata,
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input logic [SCR1_WB_WIDTH-1:0] dmem_wdata,
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output logic [SCR1_WB_WIDTH-1:0] dmem_rdata,
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output logic [SCR1_WB_WIDTH-1:0] dmem_rdata,
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output type_scr1_mem_resp_e dmem_resp,
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output logic [1:0] dmem_resp,
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// WB Interface
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// WB Interface
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output logic wbd_stb_o, // strobe/request
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output logic wbd_stb_o, // strobe/request
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output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
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output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
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output logic wbd_we_o, // write
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output logic wbd_we_o, // write
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| Line 104... |
Line 108... |
logic [SCR1_WB_WIDTH-1:0] haddr;
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logic [SCR1_WB_WIDTH-1:0] haddr;
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logic [SCR1_WB_WIDTH-1:0] hwdata;
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logic [SCR1_WB_WIDTH-1:0] hwdata;
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} type_scr1_req_fifo_s;
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} type_scr1_req_fifo_s;
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typedef struct packed {
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typedef struct packed {
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logic hwrite;
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logic [2:0] hwidth;
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logic [2:0] hwidth;
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logic [1:0] haddr;
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logic [1:0] haddr;
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} type_scr1_data_fifo_s;
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} type_scr1_data_fifo_s;
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typedef struct packed {
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typedef struct packed {
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| Line 120... |
Line 123... |
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local functions
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// Local functions
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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function automatic logic [2:0] scr1_conv_mem2wb_width (
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function automatic logic [2:0] scr1_conv_mem2wb_width (
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input type_scr1_mem_width_e dmem_width
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input logic [1:0] dmem_width
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);
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);
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logic [2:0] tmp;
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logic [2:0] tmp;
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begin
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begin
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case (dmem_width)
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case (dmem_width)
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SCR1_MEM_WIDTH_BYTE : begin
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SCR1_MEM_WIDTH_BYTE : begin
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| Line 144... |
Line 147... |
end
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end
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endfunction
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endfunction
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function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
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function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
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input logic [1:0] dmem_addr,
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input logic [1:0] dmem_addr,
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input type_scr1_mem_width_e dmem_width,
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input logic [1:0] dmem_width,
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input logic [SCR1_WB_WIDTH-1:0] dmem_wdata
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input logic [SCR1_WB_WIDTH-1:0] dmem_wdata
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);
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);
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logic [SCR1_WB_WIDTH-1:0] tmp;
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logic [SCR1_WB_WIDTH-1:0] tmp;
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begin
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begin
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tmp = 'x;
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tmp = 'x;
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| Line 257... |
Line 260... |
// Interface to Core
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// Interface to Core
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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assign dmem_req_ack = ~req_fifo_full;
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assign dmem_req_ack = ~req_fifo_full;
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assign req_fifo_wr = ~req_fifo_full & dmem_req;
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assign req_fifo_wr = ~req_fifo_full & dmem_req;
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assign dmem_rdata = scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
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assign dmem_rdata = (resp_fifo_hready) ? scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata) : 'h0;
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assign dmem_resp = (resp_fifo_hready)
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assign dmem_resp = (resp_fifo_hready)
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? (resp_fifo.hresp == 1'b1)
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? (resp_fifo.hresp == 1'b1)
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? SCR1_MEM_RESP_RDY_OK
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? SCR1_MEM_RESP_RDY_OK
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: SCR1_MEM_RESP_RDY_ER
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: SCR1_MEM_RESP_RDY_ER
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| Line 427... |
Line 430... |
end
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end
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (wbd_ack_i) begin
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if (wbd_ack_i) begin
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resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
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resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
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resp_fifo.hwidth <= data_fifo.hwidth;
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resp_fifo.hwidth <= hwidth_out;
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resp_fifo.haddr <= data_fifo.haddr;
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resp_fifo.haddr <= haddr_out[1:0];
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resp_fifo.hrdata <= wbd_dat_i;
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resp_fifo.hrdata <= (wbd_we_o) ? 'h0: wbd_dat_i;
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end
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end
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end
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end
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assign wbd_stb_o = ~req_fifo_empty;
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assign wbd_stb_o = ~req_fifo_empty;
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assign wbd_adr_o = haddr_out;
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assign wbd_we_o = hwrite_out;
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// To avoid unknown progating the design, driven zero when fifo is empty
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assign wbd_dat_o = hwdata_out;
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assign wbd_adr_o = (req_fifo_empty) ? 'h0 : haddr_out;
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assign wbd_sel_o = hbel_out;
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assign wbd_we_o = (req_fifo_empty) ? 'h0 : hwrite_out;
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assign wbd_dat_o = (req_fifo_empty) ? 'h0 : hwdata_out;
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assign wbd_sel_o = (req_fifo_empty) ? 'h0 : hbel_out;
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`endif // SCR1_DMEM_WB_IN_BP
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`endif // SCR1_DMEM_WB_IN_BP
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