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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_imem_ahb.sv] - Diff between revs 11 and 21

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Rev 11 Rev 21
Line 14... Line 14...
    // Core Interface
    // Core Interface
    output  logic                           imem_req_ack,
    output  logic                           imem_req_ack,
    input   logic                           imem_req,
    input   logic                           imem_req,
    input   logic   [SCR1_AHB_WIDTH-1:0]    imem_addr,
    input   logic   [SCR1_AHB_WIDTH-1:0]    imem_addr,
    output  logic   [SCR1_AHB_WIDTH-1:0]    imem_rdata,
    output  logic   [SCR1_AHB_WIDTH-1:0]    imem_rdata,
    output  type_scr1_mem_resp_e            imem_resp,
    output  logic [1:0]                     imem_resp,
 
 
    // AHB Interface
    // AHB Interface
    output  logic   [3:0]                   hprot,
    output  logic   [3:0]                   hprot,
    output  logic   [2:0]                   hburst,
    output  logic   [2:0]                   hburst,
    output  logic   [2:0]                   hsize,
    output  logic   [2:0]                   hsize,

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