/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @file
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/// @brief Instruction memory AHB bridge
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/// @brief Instruction memory AHB bridge
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///
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///
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`include "scr1_ahb.svh"
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`include "scr1_ahb.svh"
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`include "scr1_memif.svh"
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`include "scr1_memif.svh"
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module scr1_imem_ahb (
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module scr1_imem_ahb (
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// Control Signals
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// Control Signals
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input logic rst_n,
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input logic rst_n,
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input logic clk,
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input logic clk,
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// Core Interface
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// Core Interface
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output logic imem_req_ack,
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output logic imem_req_ack,
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input logic imem_req,
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input logic imem_req,
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input logic [SCR1_AHB_WIDTH-1:0] imem_addr,
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input logic [SCR1_AHB_WIDTH-1:0] imem_addr,
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output logic [SCR1_AHB_WIDTH-1:0] imem_rdata,
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output logic [SCR1_AHB_WIDTH-1:0] imem_rdata,
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output type_scr1_mem_resp_e imem_resp,
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output logic [1:0] imem_resp,
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// AHB Interface
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// AHB Interface
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output logic [3:0] hprot,
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output logic [3:0] hprot,
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output logic [2:0] hburst,
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output logic [2:0] hburst,
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output logic [2:0] hsize,
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output logic [2:0] hsize,
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output logic [1:0] htrans,
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output logic [1:0] htrans,
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output logic hmastlock,
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output logic hmastlock,
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output logic [SCR1_AHB_WIDTH-1:0] haddr,
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output logic [SCR1_AHB_WIDTH-1:0] haddr,
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input logic hready,
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input logic hready,
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input logic [SCR1_AHB_WIDTH-1:0] hrdata,
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input logic [SCR1_AHB_WIDTH-1:0] hrdata,
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input logic hresp
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input logic hresp
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);
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);
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local parameters declaration
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// Local parameters declaration
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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`ifndef SCR1_IMEM_AHB_OUT_BP
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`ifndef SCR1_IMEM_AHB_OUT_BP
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localparam SCR1_FIFO_WIDTH = 2;
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localparam SCR1_FIFO_WIDTH = 2;
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localparam SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
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localparam SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
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`endif // SCR1_IMEM_AHB_OUT_BP
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`endif // SCR1_IMEM_AHB_OUT_BP
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local types declaration
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// Local types declaration
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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typedef enum logic {
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typedef enum logic {
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SCR1_FSM_ADDR = 1'b0,
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SCR1_FSM_ADDR = 1'b0,
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SCR1_FSM_DATA = 1'b1,
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SCR1_FSM_DATA = 1'b1,
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SCR1_FSM_ERR = 1'bx
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SCR1_FSM_ERR = 1'bx
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} type_scr1_fsm_e;
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} type_scr1_fsm_e;
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typedef struct packed {
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typedef struct packed {
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logic [SCR1_AHB_WIDTH-1:0] haddr;
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logic [SCR1_AHB_WIDTH-1:0] haddr;
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} type_scr1_req_fifo_s;
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} type_scr1_req_fifo_s;
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typedef struct packed {
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typedef struct packed {
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logic hresp;
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logic hresp;
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logic [SCR1_AHB_WIDTH-1:0] hrdata;
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logic [SCR1_AHB_WIDTH-1:0] hrdata;
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} type_scr1_resp_fifo_s;
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} type_scr1_resp_fifo_s;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local signal declaration
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// Local signal declaration
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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type_scr1_fsm_e fsm;
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type_scr1_fsm_e fsm;
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logic req_fifo_rd;
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logic req_fifo_rd;
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logic req_fifo_wr;
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logic req_fifo_wr;
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logic req_fifo_up;
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logic req_fifo_up;
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`ifdef SCR1_IMEM_AHB_OUT_BP
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`ifdef SCR1_IMEM_AHB_OUT_BP
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type_scr1_req_fifo_s req_fifo_r;
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type_scr1_req_fifo_s req_fifo_r;
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type_scr1_req_fifo_s [0:0] req_fifo;
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type_scr1_req_fifo_s [0:0] req_fifo;
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`else // SCR1_IMEM_AHB_OUT_BP
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`else // SCR1_IMEM_AHB_OUT_BP
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type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
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type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
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type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
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type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
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logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
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logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
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logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
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logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
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`endif // SCR1_IMEM_AHB_OUT_BP
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`endif // SCR1_IMEM_AHB_OUT_BP
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logic req_fifo_empty;
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logic req_fifo_empty;
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logic req_fifo_full;
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logic req_fifo_full;
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type_scr1_resp_fifo_s resp_fifo;
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type_scr1_resp_fifo_s resp_fifo;
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logic resp_fifo_hready;
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logic resp_fifo_hready;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Interface to Core
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// Interface to Core
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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assign imem_req_ack = ~req_fifo_full;
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assign imem_req_ack = ~req_fifo_full;
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assign req_fifo_wr = ~req_fifo_full & imem_req;
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assign req_fifo_wr = ~req_fifo_full & imem_req;
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assign imem_rdata = resp_fifo.hrdata;
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assign imem_rdata = resp_fifo.hrdata;
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assign imem_resp = (resp_fifo_hready)
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assign imem_resp = (resp_fifo_hready)
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? (resp_fifo.hresp == SCR1_HRESP_OKAY)
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? (resp_fifo.hresp == SCR1_HRESP_OKAY)
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? SCR1_MEM_RESP_RDY_OK
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? SCR1_MEM_RESP_RDY_OK
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: SCR1_MEM_RESP_RDY_ER
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: SCR1_MEM_RESP_RDY_ER
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: SCR1_MEM_RESP_NOTRDY;
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: SCR1_MEM_RESP_NOTRDY;
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// REQ_FIFO
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// REQ_FIFO
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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`ifdef SCR1_IMEM_AHB_OUT_BP
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`ifdef SCR1_IMEM_AHB_OUT_BP
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always_ff @(negedge rst_n, posedge clk) begin
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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if (~rst_n) begin
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req_fifo_full <= 1'b0;
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req_fifo_full <= 1'b0;
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end else begin
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end else begin
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if (~req_fifo_full) begin
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if (~req_fifo_full) begin
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req_fifo_full <= imem_req & ~req_fifo_rd;
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req_fifo_full <= imem_req & ~req_fifo_rd;
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end else begin
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end else begin
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req_fifo_full <= ~req_fifo_rd;
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req_fifo_full <= ~req_fifo_rd;
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end
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end
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end
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end
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end
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end
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assign req_fifo_empty = ~(req_fifo_full | imem_req);
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assign req_fifo_empty = ~(req_fifo_full | imem_req);
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assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
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assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (req_fifo_up) begin
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if (req_fifo_up) begin
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req_fifo_r.haddr <= imem_addr;
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req_fifo_r.haddr <= imem_addr;
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end
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end
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end
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end
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assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
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assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
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`else // SCR1_IMEM_AHB_OUT_BP
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`else // SCR1_IMEM_AHB_OUT_BP
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always_comb begin
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always_comb begin
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req_fifo_up = 1'b0;
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req_fifo_up = 1'b0;
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req_fifo_cnt_new = req_fifo_cnt;
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req_fifo_cnt_new = req_fifo_cnt;
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req_fifo_new = req_fifo;
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req_fifo_new = req_fifo;
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case ({req_fifo_rd, req_fifo_wr})
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case ({req_fifo_rd, req_fifo_wr})
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2'b00 : begin
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2'b00 : begin
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// nothing todo
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// nothing todo
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end
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end
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2'b01: begin
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2'b01: begin
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// FIFO write
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// FIFO write
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req_fifo_up = 1'b1;
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req_fifo_up = 1'b1;
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req_fifo_new[req_fifo_cnt].haddr = imem_addr;
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req_fifo_new[req_fifo_cnt].haddr = imem_addr;
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req_fifo_cnt_new = req_fifo_cnt + 1'b1;
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req_fifo_cnt_new = req_fifo_cnt + 1'b1;
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end
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end
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2'b10 : begin
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2'b10 : begin
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// FIFO read
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// FIFO read
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req_fifo_up = 1'b1;
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req_fifo_up = 1'b1;
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req_fifo_new[0] = req_fifo_new[1];
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req_fifo_new[0] = req_fifo_new[1];
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req_fifo_new[1].haddr = 'x;
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req_fifo_new[1].haddr = 'x;
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req_fifo_cnt_new = req_fifo_cnt - 1'b1;
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req_fifo_cnt_new = req_fifo_cnt - 1'b1;
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end
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end
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2'b11 : begin
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2'b11 : begin
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// Read and Write FIFO. It is possible only when fifo_cnt = 1
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// Read and Write FIFO. It is possible only when fifo_cnt = 1
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req_fifo_up = 1'b1;
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req_fifo_up = 1'b1;
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req_fifo_new[0].haddr = imem_addr;
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req_fifo_new[0].haddr = imem_addr;
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end
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end
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default : begin
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default : begin
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req_fifo_up = 'x;
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req_fifo_up = 'x;
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req_fifo_cnt_new = 'x;
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req_fifo_cnt_new = 'x;
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req_fifo_new = 'x;
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req_fifo_new = 'x;
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end
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end
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endcase
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endcase
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end
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end
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always_ff @(negedge rst_n, posedge clk) begin
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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if (~rst_n) begin
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req_fifo_cnt <= '0;
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req_fifo_cnt <= '0;
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end else begin
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end else begin
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if (req_fifo_up) begin
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if (req_fifo_up) begin
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req_fifo_cnt <= req_fifo_cnt_new;
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req_fifo_cnt <= req_fifo_cnt_new;
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end
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end
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end
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end
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end
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end
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assign req_fifo_full = (req_fifo_cnt == SCR1_FIFO_WIDTH);
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assign req_fifo_full = (req_fifo_cnt == SCR1_FIFO_WIDTH);
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assign req_fifo_empty = ~(|req_fifo_cnt);
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assign req_fifo_empty = ~(|req_fifo_cnt);
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (req_fifo_up) begin
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if (req_fifo_up) begin
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req_fifo <= req_fifo_new;
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req_fifo <= req_fifo_new;
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end
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end
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end
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end
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`endif // SCR1_IMEM_AHB_OUT_BP
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`endif // SCR1_IMEM_AHB_OUT_BP
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// FSM
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// FSM
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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always_ff @(negedge rst_n, posedge clk) begin
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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if (~rst_n) begin
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fsm <= SCR1_FSM_ADDR;
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fsm <= SCR1_FSM_ADDR;
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end else begin
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end else begin
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case (fsm)
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case (fsm)
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SCR1_FSM_ADDR : begin
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SCR1_FSM_ADDR : begin
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if (hready) begin
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if (hready) begin
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fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
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fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
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end
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end
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end
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end
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SCR1_FSM_DATA : begin
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SCR1_FSM_DATA : begin
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if (hready) begin
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if (hready) begin
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if (hresp == SCR1_HRESP_OKAY) begin
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if (hresp == SCR1_HRESP_OKAY) begin
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fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
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fsm <= (req_fifo_empty) ? SCR1_FSM_ADDR : SCR1_FSM_DATA;
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end else begin
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end else begin
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fsm <= SCR1_FSM_ADDR;
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fsm <= SCR1_FSM_ADDR;
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end
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end
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end
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end
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end
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end
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default : begin
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default : begin
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fsm <= SCR1_FSM_ERR;
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fsm <= SCR1_FSM_ERR;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always_comb begin
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always_comb begin
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req_fifo_rd = 1'b0;
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req_fifo_rd = 1'b0;
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case (fsm)
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case (fsm)
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SCR1_FSM_ADDR : begin
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SCR1_FSM_ADDR : begin
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if (hready) begin
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if (hready) begin
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req_fifo_rd = ~req_fifo_empty;
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req_fifo_rd = ~req_fifo_empty;
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end
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end
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end
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end
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SCR1_FSM_DATA : begin
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SCR1_FSM_DATA : begin
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if (hready) begin
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if (hready) begin
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req_fifo_rd = ~req_fifo_empty & (hresp == SCR1_HRESP_OKAY);
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req_fifo_rd = ~req_fifo_empty & (hresp == SCR1_HRESP_OKAY);
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end
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end
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end
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end
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default : begin
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default : begin
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req_fifo_rd = 1'bx;
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req_fifo_rd = 1'bx;
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end
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end
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endcase
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endcase
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end
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end
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// FIFO response
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// FIFO response
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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`ifdef SCR1_IMEM_AHB_IN_BP
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`ifdef SCR1_IMEM_AHB_IN_BP
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assign resp_fifo_hready = (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
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assign resp_fifo_hready = (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
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assign resp_fifo.hresp = hresp;
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assign resp_fifo.hresp = hresp;
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assign resp_fifo.hrdata = hrdata;
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assign resp_fifo.hrdata = hrdata;
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`else // SCR1_IMEM_AHB_IN_BP
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`else // SCR1_IMEM_AHB_IN_BP
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always_ff @(negedge rst_n, posedge clk) begin
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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if (~rst_n) begin
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resp_fifo_hready <= 1'b0;
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resp_fifo_hready <= 1'b0;
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end else begin
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end else begin
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resp_fifo_hready <= (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
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resp_fifo_hready <= (fsm == SCR1_FSM_DATA) ? hready : 1'b0;
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end
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end
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end
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end
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (hready & (fsm == SCR1_FSM_DATA)) begin
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if (hready & (fsm == SCR1_FSM_DATA)) begin
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resp_fifo.hresp <= hresp;
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resp_fifo.hresp <= hresp;
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resp_fifo.hrdata <= hrdata;
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resp_fifo.hrdata <= hrdata;
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end
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end
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end
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end
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`endif // SCR1_IMEM_AHB_IN_BP
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`endif // SCR1_IMEM_AHB_IN_BP
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Interface to AHB
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// Interface to AHB
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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assign hprot[SCR1_HPROT_DATA] = 1'b0;
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assign hprot[SCR1_HPROT_DATA] = 1'b0;
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assign hprot[SCR1_HPROT_PRV] = 1'b0;
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assign hprot[SCR1_HPROT_PRV] = 1'b0;
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assign hprot[SCR1_HPROT_BUF] = 1'b0;
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assign hprot[SCR1_HPROT_BUF] = 1'b0;
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assign hprot[SCR1_HPROT_CACHE] = 1'b0;
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assign hprot[SCR1_HPROT_CACHE] = 1'b0;
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|
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assign hburst = SCR1_HBURST_SINGLE;
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assign hburst = SCR1_HBURST_SINGLE;
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assign hsize = SCR1_HSIZE_32B;
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assign hsize = SCR1_HSIZE_32B;
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assign hmastlock = 1'b0;
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assign hmastlock = 1'b0;
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always_comb begin
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always_comb begin
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htrans = SCR1_HTRANS_IDLE;
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htrans = SCR1_HTRANS_IDLE;
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case (fsm)
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case (fsm)
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SCR1_FSM_ADDR : begin
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SCR1_FSM_ADDR : begin
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if (~req_fifo_empty) begin
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if (~req_fifo_empty) begin
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htrans = SCR1_HTRANS_NONSEQ;
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htrans = SCR1_HTRANS_NONSEQ;
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end
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end
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end
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end
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SCR1_FSM_DATA : begin
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SCR1_FSM_DATA : begin
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if (hready) begin
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if (hready) begin
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if (hresp == SCR1_HRESP_OKAY) begin
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if (hresp == SCR1_HRESP_OKAY) begin
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if (~req_fifo_empty) begin
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if (~req_fifo_empty) begin
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htrans = SCR1_HTRANS_NONSEQ;
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htrans = SCR1_HTRANS_NONSEQ;
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end
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end
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end
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end
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end
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end
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end
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end
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default : begin
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default : begin
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htrans = SCR1_HTRANS_ERR;
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htrans = SCR1_HTRANS_ERR;
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end
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end
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endcase
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endcase
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end
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end
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|
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assign haddr = req_fifo[0].haddr;
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assign haddr = req_fifo[0].haddr;
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|
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`ifdef SCR1_TRGT_SIMULATION
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`ifdef SCR1_TRGT_SIMULATION
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//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
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// Assertion
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// Assertion
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
|
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// Check Core interface
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// Check Core interface
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SCR1_SVA_IMEM_AHB_BRIDGE_REQ_XCHECK : assert property (
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SCR1_SVA_IMEM_AHB_BRIDGE_REQ_XCHECK : assert property (
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@(negedge clk) disable iff (~rst_n)
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@(negedge clk) disable iff (~rst_n)
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!$isunknown(imem_req)
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!$isunknown(imem_req)
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) else $error("IMEM AHB bridge Error: imem_req has unknown values");
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) else $error("IMEM AHB bridge Error: imem_req has unknown values");
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|
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SCR1_IMEM_AHB_BRIDGE_ADDR_XCHECK : assert property (
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SCR1_IMEM_AHB_BRIDGE_ADDR_XCHECK : assert property (
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@(negedge clk) disable iff (~rst_n)
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@(negedge clk) disable iff (~rst_n)
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imem_req |-> !$isunknown(imem_addr)
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imem_req |-> !$isunknown(imem_addr)
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) else $error("IMEM AHB bridge Error: imem_addr has unknown values");
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) else $error("IMEM AHB bridge Error: imem_addr has unknown values");
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|
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SCR1_IMEM_AHB_BRIDGE_ADDR_ALLIGN : assert property (
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SCR1_IMEM_AHB_BRIDGE_ADDR_ALLIGN : assert property (
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@(negedge clk) disable iff (~rst_n)
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@(negedge clk) disable iff (~rst_n)
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imem_req |-> (imem_addr[1:0] == '0)
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imem_req |-> (imem_addr[1:0] == '0)
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) else $error("IMEM AHB bridge Error: imem_addr has unalign values");
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) else $error("IMEM AHB bridge Error: imem_addr has unalign values");
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|
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// Check AHB interface
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// Check AHB interface
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SCR1_IMEM_AHB_BRIDGE_HREADY_XCHECK : assert property (
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SCR1_IMEM_AHB_BRIDGE_HREADY_XCHECK : assert property (
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@(negedge clk) disable iff (~rst_n)
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@(negedge clk) disable iff (~rst_n)
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!$isunknown(hready)
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!$isunknown(hready)
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) else $error("IMEM AHB bridge Error: hready has unknown values");
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) else $error("IMEM AHB bridge Error: hready has unknown values");
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|
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SCR1_IMEM_AHB_BRIDGE_HRESP_XCHECK : assert property (
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SCR1_IMEM_AHB_BRIDGE_HRESP_XCHECK : assert property (
|
@(negedge clk) disable iff (~rst_n)
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@(negedge clk) disable iff (~rst_n)
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!$isunknown(hresp)
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!$isunknown(hresp)
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) else $error("IMEM AHB bridge Error: hresp has unknown values");
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) else $error("IMEM AHB bridge Error: hresp has unknown values");
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|
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`endif // SCR1_TRGT_SIMULATION
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`endif // SCR1_TRGT_SIMULATION
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|
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endmodule : scr1_imem_ahb
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endmodule : scr1_imem_ahb
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|
|
