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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_imem_wb.sv] - Diff between revs 11 and 19

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Rev 11 Rev 19
Line 166... Line 166...
 
 
`else // SCR1_IMEM_WB_OUT_BP
`else // SCR1_IMEM_WB_OUT_BP
 
 
 
 
 sync_fifo #(
 sync_fifo #(
      .DATA_WIDTH(SCR1_WB_WIDTH), // Data Width
      .W(SCR1_WB_WIDTH), // Data Width
      .ADDR_WIDTH(1),   // Address Width
      .D(2)    // FIFO DEPTH
      .FIFO_DEPTH(2)    // FIFO DEPTH
 
     )   u_req_fifo(
     )   u_req_fifo(
 
 
       .dout      (req_fifo_dout  ),
       .rd_data    (req_fifo_dout  ),
 
 
       .rstn      (rst_n          ),
       .reset_n   (rst_n          ),
       .clk       (clk            ),
       .clk       (clk            ),
       .wr_en     (req_fifo_wr    ), // Write
       .wr_en     (req_fifo_wr    ), // Write
       .rd_en     (req_fifo_rd    ), // Read
       .rd_en     (req_fifo_rd    ), // Read
       .din       (imem_addr      ),
       .wr_data   (imem_addr      ),
       .full      (req_fifo_full  ),
       .full      (req_fifo_full  ),
       .empty     (req_fifo_empty )
       .empty     (req_fifo_empty )
);
);
 
 
 
 

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