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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_imem_wb.sv] - Diff between revs 19 and 21

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Rev 19 Rev 21
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////                                                              ////
////  Revision :                                                  ////
////  Revision :                                                  ////
////     v0:    June 7, 2021, Dinesh A                            ////
////     v0:    June 7, 2021, Dinesh A                            ////
////             wishbone integration                             ////
////             wishbone integration                             ////
 
////     v1:    June 9, 2021, Dinesh A                            ////
 
////              On power up, wishbone output are unkown as it   ////
 
////              driven from fifo output. To avoid unknown       ////
 
////              propgation, we are driving 'h0 when fifo empty  ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
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    // Core Interface
    // Core Interface
    output  logic                           imem_req_ack,
    output  logic                           imem_req_ack,
    input   logic                           imem_req,
    input   logic                           imem_req,
    input   logic   [SCR1_WB_WIDTH-1:0]     imem_addr,
    input   logic   [SCR1_WB_WIDTH-1:0]     imem_addr,
    output  logic   [SCR1_WB_WIDTH-1:0]     imem_rdata,
    output  logic   [SCR1_WB_WIDTH-1:0]     imem_rdata,
    output  type_scr1_mem_resp_e            imem_resp,
    output  logic [1:0]                     imem_resp,
 
 
    // WB Interface
    // WB Interface
    output  logic                           wbd_stb_o, // strobe/request
    output  logic                           wbd_stb_o, // strobe/request
    output  logic   [SCR1_WB_WIDTH-1:0]     wbd_adr_o, // address
    output  logic   [SCR1_WB_WIDTH-1:0]     wbd_adr_o, // address
    output  logic                           wbd_we_o,  // write
    output  logic                           wbd_we_o,  // write
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        resp_fifo.hrdata <= wbd_dat_i;
        resp_fifo.hrdata <= wbd_dat_i;
    end
    end
end
end
 
 
assign wbd_stb_o    = ~req_fifo_empty;
assign wbd_stb_o    = ~req_fifo_empty;
assign wbd_adr_o    = req_fifo_dout;
// On Power, to avoid unknow propgating the value
 
assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout;
assign wbd_we_o     = 0; // Only Read supported
assign wbd_we_o     = 0; // Only Read supported
assign wbd_dat_o    = 32'h0; // No Write
assign wbd_dat_o    = 32'h0; // No Write
assign wbd_sel_o    = 4'b1111; // Only Read allowed in imem i/f
assign wbd_sel_o    = 4'b1111; // Only Read allowed in imem i/f
`endif // SCR1_IMEM_WB_IN_BP
`endif // SCR1_IMEM_WB_IN_BP
 
 

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