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Line 19... |
// Core instruction interface
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// Core instruction interface
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output logic imem_req_ack,
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output logic imem_req_ack,
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input logic imem_req,
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input logic imem_req,
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input logic [`SCR1_IMEM_AWIDTH-1:0] imem_addr,
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input logic [`SCR1_IMEM_AWIDTH-1:0] imem_addr,
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output logic [`SCR1_IMEM_DWIDTH-1:0] imem_rdata,
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output logic [`SCR1_IMEM_DWIDTH-1:0] imem_rdata,
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output type_scr1_mem_resp_e imem_resp,
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output logic [1:0] imem_resp,
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// Core data interface
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// Core data interface
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output logic dmem_req_ack,
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output logic dmem_req_ack,
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input logic dmem_req,
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input logic dmem_req,
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input type_scr1_mem_cmd_e dmem_cmd,
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input logic dmem_cmd,
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input type_scr1_mem_width_e dmem_width,
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input logic [1:0] dmem_width,
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input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
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input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
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output type_scr1_mem_resp_e dmem_resp
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output logic [1:0] dmem_resp
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);
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);
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local signal declaration
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// Local signal declaration
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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